WED3C7410E16M400BC 데이터 시트보기 (PDF) - White Electronic Designs Corporation

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WED3C7410E16M400BC

RISC Microprocessor Multichip Package

White Electronic Designs Corporation 

White Electronic Designs WED3C7410E16M-XBX

PLL POWER SUPPLY FILTERING

The AVCC and L2AVCC power signals are provided on

the WED3C7410E16M-XBX to provide power to the clock

generation phase-locked loop and L2 cache delay-locked

loop respectively. To ensure stability of the internal clock,

the power supplied to the AVCC input signal should be

filtered of any noise in the 500kHz to 10 MHz resonant

frequency range of the PLL. A circuit similar to the

one shown in Figure 6 using surface mount capacitors

with minimum Effective Series Inductance (ESL) is

recommended. Multiple small capacitors of equal value are

recommended over a single large value capacitor.

The circuit should be placed as close as possible to the

AVCC pin to minimize noise coupled from nearby circuits.

An identical but separate circuit should be placed as close

as possible to the L2AVCC pin. It is often possible to route

directly from the capacitors to the AVCC pin, which is on the

periphery of the 255 BGA footprint, without the inductance

of vias. The L2AVCC pin may be more difficult to route but

is proportionately less critical.

FIGURE 6 – POWER SUPPLY FILTER CIRCUIT

VCC

10 Ω

2.2 µF

2.2 µF

AVCC (or L2AVCC)

Low ESL surface mount capacitors

GND

May 2006

Rev. 9

11

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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