WM5620 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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WM5620 Datasheet PDF : 14 Pages
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WM5620L, WM5620
Pin Descriptions
Pin
Name
1
GND
2
RefA
3
RefB
4
RefC
5
RefD
6
Data
7
Clk
8
Load
9
DACD
10
DACC
11
DACB
12
DACA
13
LDAC
14
VDD
Type
Supply
Analogue input
Analogue input
Analogue input
Analogue input
Digital input
Digital input
Digital input
Analogue output
Analogue output
Analogue output
Analogue output
Digital input
Supply
Function
Ground return and reference terminal
Reference voltage input to DACA
Reference voltage input to DACB
Reference voltage input to DACC
Reference voltage input to DACD
Serial interface data
Serial interface clock, negative edge sensitive
Serial interface load
DAC D output
DAC C output
DAC B output
DAC A output
DAC update latch control
positive supply voltage
Functional Description
DAC operation
Each of WM5620/L 's four digital to analogue converters
(DACs) are implemented using a single resistor string with
256 taps corresponding to each of the input 8-bit codes.
One end of a resistor string is connected to the GND pin
and the other end is driven from the output of a reference
input buffer. The use of a resistor string guarantees
monotonicity of the DAC's output voltage. Linearity depends
upon the matching of the resistor string's individual elements
and the performance of the output buffer. The reference input
buffers present a high impedance to reference sources.
Each DAC has a voltage output amplifier which is
programmable for gains of x1 or x 2 through the serial
interface. The DAC output amplifiers feature rail to rail
output stages, allowing outputs over the full supply voltage
range to be achieved with a x 2 gain setting and a VDD/2
reference voltage input. Used in this way a slight
degradation in linearity will occur as the output voltage
approaches VDD.
A power-on-reset activates at power up resetting the DACs
inputs to code 0. Each output voltage is given by:
Vout = Vref x CODE/256 x (1 + RNG)
Where: RNG controls the output gains of x 1 and x 2
CODE is the range 0 to 255
Data Interface
WM5620/L's four double buffered DAC inputs allow
several ways of controlling the update of each DAC's
output.
Serial data is input, MSB first, into the DATA input pin using
CLK, LOAD and LDAC control inputs and comprises 2 DAC
address bits, an output range (RNG) bit and 8 DAC input
bits.
With the LOAD pin high data is clocked into the DATA pin
on each falling edge of CLK. Any number of data bits may
be clocked in, only the last 11 bits are used. When all data
bits have been clocked in, a falling edge at the LOAD pin
latches the data and RNG bits into the correct 9 bit input
latch using the 2 bit DAC address.
If the LDAC input pin is low, the second latch at the DAC
input is transparent, and the DAC input and RNG bit will be
updated on the falling edge of LOAD simultaneously with
the input latch, as shown in figure 1. If the LDAC input is high
during serial data input, as shown in figure 2, the falling edge
of the LOAD input stores the data in the addressed input
latch. The falling edge of LDAC updates the second latches
from the input latches and hence the DAC outputs.
10
Wolfson Microelectronics
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