WM8143-10 데이터 시트보기 (PDF) - Wolfson Microelectronics plc

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WM8143-10

10-bit/6MSPS CCD Signal Processor

Wolfson Microelectronics plc 

WM8143-10

For the input stage, the final analogue voltage applied

to the ADC can be expressed as:

Production Data

dependent on the type of sampling selected and the

polarity of the input video signal.

VADC = G * (VVS − VRS) + [(1 − 2 * DSIGN) * DAC_CODE * ] VMID + VMID

255

2

Where VADC is the voltage applied, to the ADC

G is the programmed gain

VVS is the voltage of the video sample.

VRS is the voltage of the reset sample,

DSIGN is the Offset DAC sign bit

DAC_CODE is the offset DAC value.

VMID is the WM8143-10 generated VMID voltage.

The ADC has a lower reference of VRB (typically 1.5 V)

and an upper reference of VRT (typically 3.5 V). When

an ADC input voltage is applied to the ADC equal to

VRB the resulting code is 000(hex). When an ADC input

voltage is applied to the ADC equal to VRT the resulting

code is 3FF(hex).

Reset Level Clamp

Both CDS and Single Ended operation can be used

with Reset Level Clamping. A typical input

configuration is shown in Figure 4.

WM8143-10

RINP

Cin

S/H

VS

S/H

VRLC

RS

VMID

+

Gain=G

-

MCLK

VSMP

VS

CL

00

RS

CL

01

(default) RS

CL

10

RS

CL

11

RS

Figure 5 Reset Sample and Clamp Timing

For CDS operation it is important to match the clamp

voltage to the amplitude and polarity of the video

signal. This will allow the best use of the wide input

common-mode range offered by the WM8143-10. If the

input video is positive going it is advisable to clamp to

VCL (Lower clamp voltage). If the video is negative

going it is advisable to clamp to VCU (Upper clamp

voltage). Regardless of where the video is clamped the

offset DAC is programmed to move the ADC output

corresponding to the reset level to an appropriate value

to maximise the ADC dynamic range. For Single Ended

operation it is recommended that the clamp voltage is

set to VCM (middle clamp voltage).

Figure 4 Typical Input Configuration Using Reset

Level Clamping

The position of the clamp relative to the video sample

is shown diagramatically in Figure 6 and is

programmable by CDSREF1-0 (see Table 6). By

default, the reset sample occurs on the fourth MCLK

rising edge after VSMP. The relative timing between the

reset sample (and CL) and video sample can be altered

as shown in Figure 5. When the clamp pulse is active

the voltage on the WM8143-10 side of Cin, i.e. RINP,

will be forced to be equal to the VRLC clamp voltage.

The VRLC clamp voltage is programmable to three

different levels via the serial interface. The voltage to

which the clamp voltage should be programmed is

VIDEO INPUT

CLAMP PULSE

Figure 6 Position of Clamp Relative to Video Input

A reset level clamp is activated if the RLC pin is high

on an MCLK rising edge (Figure 7). By default this

initiates an internal clamp pulse three MCLK pulses

later (shown as CL in Figure 5). The relationship

between CL and RS is fixed. Therefore altering the RS

position also alters the CL position (Figure 5). Table 6

shows the three possible voltages to which the reset

level can be clamped.

Wolfson Microelectronics

PD Rev 3f June 98

10

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