WM8746 데이터 시트보기 (PDF) - Wolfson Microelectronics plc

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WM8746

24-bit, 192kHz 6-Channel DAC with Volume Control

Wolfson Microelectronics plc 

WM8746

Production Data

DIGITAL AUDIO INTERFACE

Audio data is applied to the internal DAC filters via the Digital Audio Interface. Five popular interface

formats are supported:

• Left Justified mode

• Right Justified mode

• I2S mode

• DSP Mode A

• DSP Mode B

All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, except right

justified that does not support 32 bit data. DIN0/1/2 and LRCIN are sampled on the rising, or falling

edge of BCKIN.

In left justified, right justified and I2S modes, the digital audio interface receives data on the DIN0/1/2

inputs. Audio Data for each stereo channel is time multiplexed with LRCIN indicating whether the left

or right channel is present. LRCIN is also used as a timing reference to indicate the beginning or end

of the data words.

In left justified, right justified and I2S modes, the minimum number of BCKINs per LRCIN period is

twice the selected word length. LRCIN must be high for at least the word length number of BCKINs

and low for at least the same. Any mark to space ratio on LRCIN is acceptable provided the above

requirements are met. The WM8746 will automatically detect when data with a LRCIN period of

exactly 32 is sent, and select 16 bit mode - overriding any previously programmed word length. Word

length will revert to the previously programmed value if a LRCIN period other than 32 is detected.

In DSP Mode A or B, all 6 channels are time multiplexed onto DIN0. LRCIN is used as a frame sync

signal to identify the MSB of the first word. The minimum number of BCKINs per LRCIN period is 6

times the selected word length. Any mark to space ratio is acceptable on LRCIN provided the rising

edge is correctly positioned. (see Figure 7, Figure 8)

LEFT JUSTIFIED MODE

In left justified mode, the MSB is sampled on the first rising edge of BCKIN following a LRCIN

transition. LRCIN is high during the left samples and low during the right samples.

LRCIN

BCKIN

1/fs

LEFT CHANNEL

RIGHT CHANNEL

DIN0/1/2

123

MSB

n-2 n-1 n

LSB

123

MSB

Figure 4 Left Justified Mode Timing Diagram

n-2 n-1 n

LSB

w

March 2006, PD Rev 4.0

11

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