WM8771FV 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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WM8771FV Datasheet PDF : 44 Pages
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DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
ADCLRC
WM8771
CODEC DACLRC
DOUT
DIN1/2/3/4
4
DSP/
ENCODER/
DECODER
Figure 2 Audio Interface - Master Mode
WM8771
BCLK
(Output)
ADCLRC/
DACLRC
(Outputs)
DOUT
tDL
tDDA
DIN1/2/3/4
tDST
tDHT
Figure 3 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
ADCLRC/DACLRC
tDL
propagation delay from
BCLK falling edge
DOUT propagation delay
tDDA
from BCLK falling edge
DIN1/2/3/4 setup time to
tDST
BCLCK rising edge
DIN1/2/3/4 hold time from
tDHT
BCLK rising edge
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
10
ns
0
10
ns
10
ns
10
ns
Table 2 Digital Audio Data Timing – Master Mode
w
PP Rev 2.0 December 2001
9
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