WM8774 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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WM8774 Datasheet PDF : 42 Pages
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WM8774
DIGITAL AUDIO INTERFACE – SLAVE MODE
BCLK
ADCLRC
WM8774
CODEC DACLRC
DOUT
DIN
DVD
Controller
Product Preview
Figure 4 Audio Interface – Slave Mode
BCLK
tBCH
tBCL
tBCY
DACLRC/
ADCLRC
DIN
tDS
tDD
DOUT
tLRH
tDH
tLRSU
Figure 5 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise
stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
BCLK cycle time
tBCY
BCLK pulse width high
BCLK pulse width low
DACLRC/ADCLRC set-up
time to BCLK rising edge
tBCH
tBCL
tLRSU
DACLRC/ADCLRC hold
tLRH
time from BCLK rising edge
DIN set-up time to BCLK
tDS
rising edge
DIN hold time from BCLK
tDH
rising edge
DOUT propagation delay
tDD
from BCLK falling edge
TEST CONDITIONS
MIN
TYP
MAX
50
20
20
10
10
10
10
0
10
Table 3 Digital Audio Data Timing – Slave Mode
Note:
1. ADCLRC and DACLRC should be synchronous with MCLK, although the WM8774 interface is tolerant of phase
variations or jitter on these signals.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
PP Rev 1.0 June 2002
10
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