WM9704M 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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WM9704M Datasheet PDF : 37 Pages
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WM9704M
WARM RESET
SYNC
tSYNC_HIGH
tSYNC2CLK
Production Data
BIT_CLK
Figure 3 Warm Reset Timing
PARAMETER
SYNC active high pulse width
SYNC inactive to BIT_CLK
startup delay
SYMBOL
tSYNC_HIGH
tSYNC2_CLK
MIN
162.4
TYP
1.3
CLOCK SPECIFICATIONS
BIT_CLK
SYNC
tCLK_HIGH
tCLK_PERIOD
tSYNC_HIGH
tCLK_LOW
tSYNC_LOW
tSYNC_PERIOD
MAX
UNIT
µs
ns
Figure 4 Clock Specifications (50pF External Load)
PARAMETER
SYMBOL
BIT_CLK frequency
BIT_CLK period
tCLK_PERIOD
BIT_CLK output jitter
BIT_CLK high pulse width (Note 1)
BIT_CLK low pulse width (Note 1)
tCLK_HIGH
tCLK_LOW
SYNC frequency
SYNC period
tSYNC_PERIOD
SYNC high pulse width
SYNC low pulse width
tSYNC_HIGH
tSYNC_LOW
Note: Worst case duty cycle restricted to 40/60
MIN
32.56
32.56
TYP
12.288
81.4
40.7
40.7
48.0
20.8
1.3
19.5
MAX
750
48.84
48.84
UNIT
MHz
ns
ps
ns
ns
KHz
µs
µs
µs
WOLFSON MICROELECTRONICS LTD
PD Rev 3.2 January 2001
8
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