WM8783 데이터 시트보기 (PDF) - Wolfson Microelectronics plc

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WM8783

Stereo Low Power 96kHz ADC

Wolfson Microelectronics plc 

WM8783

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

MCLK

tMCLKY

tMCLKL tMCLKH

Production Data

Figure 2 Master Clock Timing

Test Conditions

AVDD = 3.3V, GND = 0V, TA = +25oC.

PARAMETER

Master Clock Timing

MCLK frequency

SYMBOL

1 / TMCLKY

MCLK duty cycle

(= TMCLKH : TMCLKL)

CONDITIONS

fs = 8kHz

fs = 16kHz

fs = 32kHz

fs = 44.1kHz

fs = 48kHz

fs = 88.2kHz

fs = 96kHz

MIN

TYP

MAX

60:40

2.048

4.096

8.192

11.2896

12.288

11.2896

12.288

40:60

UNIT

MHz

w

PD, August 2010, Rev 4.0

8

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