WM8951L 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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WM8951L Datasheet PDF : 42 Pages
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WM8951L
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
ADCLRC
WM8951L
ADC
ADCDAT
DSP
ENCODER/
DECODER
Figure 3 Master Mode Connection
BCLK
(Output)
ADCLRC
(Output)
ADCDAT
t
DL
t
DDA
Production Data
Figure 4 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD1, AVDD2, DBDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
ADCLRC propagation delay
tDL
from BCLK falling edge
ADCDAT propagation delay
tDDA
from BCLK falling edge
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
10
ns
0
15
ns
w
PD Rev 4.1 December 2007
10
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