WM8951L 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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WM8951L Datasheet PDF : 42 Pages
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Production Data
MASTER CLOCK TIMING
XTI/MCLK
tXTIL
tXTIH
tXTIY
WM8951
Figure 1 System Clock Timing Requirements
Test Conditions
AVDD1, AVDD2, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
XTI/MCLK System clock pulse
tXTIH
width high
18
ns
XTI/MCLK System clock pulse
tXTIL
width low
18
ns
XTI/MCLK System clock cycle time
tXTIY
XTI/MCLK Duty cycle
54
40:60
ns
60:40
XTI/MCLK
tCOP
CLKOUT
CLKOUT
(DIV X2)
Figure 2 Clock Out Timing Requirements
Test Conditions
AVDD1, AVDD2, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
System Clock Timing Information
CLKOUT propagation delay
tCOP
from XTI/MCLK falling edge
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
10
ns
w
PD Rev 4.1 December 2007
9
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