WM8948 데이터 시트보기 (PDF) - Wolfson Microelectronics plc

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WM8948

Stereo Low-Power CODEC with Video Buffer and Touch Panel Controller

Wolfson Microelectronics plc 

WM8948

Production Data

TABLE OF CONTENTS

DESCRIPTION .......................................................................................................1

FEATURES............................................................................................................. 1

APPLICATIONS .....................................................................................................1

TABLE OF CONTENTS .........................................................................................2

BLOCK DIAGRAM .................................................................................................5

PIN CONFIGURATION...........................................................................................6

ORDERING INFORMATION ..................................................................................6

PIN DESCRIPTION ................................................................................................7

ABSOLUTE MAXIMUM RATINGS.........................................................................8

RECOMMENDED OPERATING CONDITIONS .....................................................8

THERMAL PERFORMANCE .................................................................................9

ELECTRICAL CHARACTERISTICS ....................................................................10

TERMINOLOGY........................................................................................................... 14

TYPICAL PERFORMANCE.......................................................................................... 15

POWER CONSUMPTION............................................................................................ 16

AUDIO SIGNAL PATHS DIAGRAM .....................................................................17

SIGNAL TIMING REQUIREMENTS .....................................................................18

SYSTEM CLOCK TIMING............................................................................................ 18

AUDIO INTERFACE TIMING ....................................................................................... 18

MASTER MODE ........................................................................................................................................ 18

SLAVE MODE ........................................................................................................................................... 19

CONTROL INTERFACE TIMING ................................................................................. 20

DEVICE DESCRIPTION .......................................................................................23

INTRODUCTION.......................................................................................................... 23

ANALOGUE INPUT SIGNAL PATH ............................................................................. 24

INPUT PGA ENABLE ................................................................................................................................ 25

INPUT PGA CONFIGURATION ................................................................................................................ 25

MICROPHONE BIAS CONTROL .............................................................................................................. 26

INPUT PGA GAIN CONTROL ................................................................................................................... 26

DIGITAL MICROPHONE INTERFACE......................................................................... 29

ANALOGUE-TO-DIGITAL CONVERTER (ADC) .......................................................... 30

ADC VOLUME CONTROL ........................................................................................................................ 31

ADC HIGH PASS FILTER ......................................................................................................................... 33

DSP CORE .................................................................................................................. 34

DSP CONFIGURATION MODES .............................................................................................................. 34

LOW-PASS / HIGH-PASS FILTER (LPF/HPF) ......................................................................................... 35

3D SURROUND ........................................................................................................................................ 36

5-NOTCH FILTER ..................................................................................................................................... 36

DF1 FILTER .............................................................................................................................................. 37

RETUNETM FILTER ................................................................................................................................... 38

5-BAND EQ ............................................................................................................................................... 38

DYNAMIC RANGE CONTROL (DRC) ....................................................................................................... 39

SIGNAL ENHANCEMENT REGISTER CONTROLS ................................................................................. 39

DYNAMIC RANGE CONTROL (DRC).......................................................................... 41

DRC COMPRESSION / EXPANSION / LIMITING ..................................................................................... 41

GAIN LIMITS ............................................................................................................................................. 44

GAIN READBACK ..................................................................................................................................... 45

DYNAMIC CHARACTERISTICS ............................................................................................................... 45

ANTI-CLIP CONTROL............................................................................................................................... 47

QUICK-RELEASE CONTROL ................................................................................................................... 47

DRC INITIAL VALUE ................................................................................................................................. 48

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PD, May 2011, Rev 4.1

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