WM8953ECS 데이터 시트보기 (PDF) - Wolfson Microelectronics plc

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WM8953ECS

Low Power Stereo ADC with PLL and TDM Interface

Wolfson Microelectronics plc 

Production Data

WM8953

Test Conditions

DCVDD = 1.8V, DBVDD = 3.3V, AVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz,

PGA gain = 0dB, 24-bit audio data unless otherwise stated.

PARAMETER

TEST CONDITIONS

MIN

TYP

Analogue Reference Levels

VMID Midrail Reference Voltage

-3%

AVDD/2

Microphone Bias

Bias Voltage

3mA load current

-5%

0.9×AVDD

MBSEL=0

3mA load current

-5%

0.65×AVDD

MBSEL=1

Bias Current Source

Output Noise Density

1kHz to 20kHz

100

AVDD PSRR (217Hz)

100mV pk-pk @217Hz

45

on AVDD

Digital Input / Output

Input HIGH Level

0.7×DBVDD

Input LOW Level

Note that digital input pins should not be left unconnected / floating.

Internal pull-up/pull-down resistors may be enabled on GPIO3, GPIO4 and GPIO5 if required.

Output HIGH Level

Output LOW Level

IOL=1mA

IOH=-1mA

0.9×DBVDD

Input capacitance

10

Input leakage

-0.9

PLL

Input Frequency

PRESCALE = 0b

7.7

PRESCALE = 1b

14.4

Lock time

200

GPIO

Clock output duty cycle

SYSCLK=MCLK;

35

(Integer OPCLKDIV)

OPCLKDIV=0000

SYSCLK=MCLK;

45

OPCLKDIV=1000

SYSCLK=PLL output;

45

OPCLKDIV=0000

SYSCLK=PLL output;

45

OPCLKDIV=1000

Clock output duty cycle

SYSCLK=MCLK;

33

(Non-integer OPCLKDIV)

OPCLKDIV=0100

SYSCLK=PLL output;

33

Interrupt response time for accessory /

button detect

OPCLKDIV=0100

Input de-bounced

Input de-bounced

TOCLKSEL=1

221 / fSYSCLK

219 / fSYSCLK

Input not de-bounced

0

MAX

+3%

+5%

+5%

3

0.3×DBVDD

0.1×DBVDD

0.9

18

36

65

55

55

55

66

66

222 / fSYSCLK

220 / fSYSCLK

UNIT

V

V

V

mA

nV/√Hz

dB

V

V

V

V

pF

uA

MHz

MHz

us

%

%

%

%

%

%

s

s

s

w

PD, January 2009, Rev 4.0

11

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