X24C04-2.7 데이터 시트보기 (PDF) - Xicor -> Intersil
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X24C04-2.7 Datasheet PDF : 13 Pages
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X24C04
Figure 8. Random Read
S
S
Bus Activity: T
Master A
Slave
Address
Word
Address n
T Slave
A Address
S
T
R
R
O
T
T
P
SDA Line S
S
P
Bus Activity:
X24C04
A
A
C
C
K
K
A
C
Data n
K
Sequential Read
Sequential Read can be initiated as either a current
address read or random access read. The first word is
transmitted as with the other modes, however, the
master now responds with an acknowledge, indicating
it requires additional data. The X24C04 continues to
output data for each acknowledge received. The read
operation is terminated by the master; by not responding
with an acknowledge and by issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from n + 1. The address
counter for read operations increments all address bits,
allowing the entire memory contents to be serially read
during one operation. At the end of the address space
(address 511), the counter “rolls over” to address 0 and
the X24C04 continues to output data for each acknowl-
edge received. Refer to Figure 9 for the address,
acknowledge and data transfer sequence.
Figure 9. Sequential Read
Bus Activity: Slave
Master Address
A
A
A
S
C
C
C
T
K
K
K
O
P
SDA Line
P
Bus Activity:
X24C04
A
C
K Data n
Data n+1
Data n+2
Data n+x
Figure 10. Typical System Configuration
SDA
SCL
Master
Transmitter/
Receiver
Slave
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
VCC
Pull-Up
Resistors
REV 1.1.3 11/28/00
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Characteristics subject to change without notice. 7 of 13
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