AD6630AR 데이터 시트보기 (PDF) - Analog Devices

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AD6630AR

Differential, Low Noise IF Gain Block with Output Clamping

Analog Devices 

AD6630

SMA

CHNA

L1A

C1 C2

L1 11

VI

VO

5

SAW1

12 VI

VO

6

GND

1 2 3 4 7 8 9 10

C100

0.1␮F

L2

C101

0.1␮F

+10V

U100A

NC1 VCC1

NC2 CD1

IP2

OP

IP1

IP1B

VEE

CMD

IP2B OPB

CL1 CD2

CL2 VCC2

AD6630

11

L4

12

C104

0.1␮F

C103

0.1␮F

VI

VO

5

L6

SAW2

6

VI

VO

GND

1 2 3 4 7 8 9 10

C102

0.1␮F

TO

AD6600

Figure 9. Reference Design Schematic (One Channel)

Figure 10. Reference Design PCB Layout

+

+

DIFF

AMP

–

–

OUTPUT

AMP

+

OUTPUT

AMP

–

CLHI

CLLO

CLP

CLAMP

GENERATOR CLN

Figure 11. Functional Block Diagram

Figure 12. Reference Design Component Placement (Two

Channels Shown)

IP1

TO OUTPUT

AMPLIFIER

IP2

VCC

200⍀ 200⍀

BIAS

200⍀ 200⍀

IP1

TO OUTPUT

AMPLIFIER

IP2

VEE

Figure 13. Equivalent Input Circuit

–6–

REV. 0

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