CS8411 데이터 시트보기 (PDF) - Unspecified

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CS8411

Digital Audio Interface Receiver

Unspecified 

CS8411 CS8412

SWITCHING CHARACTERISTICS - SERIAL PORTS

(TA = 25 °C for suffixes '-CP' and '-CS'; TA = -40 to 85 °C for suffixes '-IP' and '-IS';

VD+, VA+ = 5V ± 10%; Inputs: Logic 0 = DGND, logic 1 = VD+; CL = 20 pF)

Parameter

Symbol

SCK Frequency

Master Mode Notes 6, 7 fsck

Slave Mode Note 7

SCK falling to FSYNC delay

Master Mode Notes 7, 8

SCK Pulse Width Low

Slave Mode Note 7

SCK Pulse Width High

Slave Mode Note 7

SCK rising to FSYNC edge delay Slave Mode Notes 7,8

FSYNC edge to SCK rising setup Slave Mode Notes 7,8

SCK falling (rising) to SDATA valid

Note 8

C, U, CBL valid to FSYNC edge CS8412

Note 8

MCK to FSYNC edge delay

FSYNC from RXN/RXP

tsfdm

tsckl

tsckh

tsfds

tfss

tssv

tcuvf

tmfd

Min

OWRx32

-20

40

40

20

20

Typ

OWRx32

1/fsck

15

Max

128xFs

20

20

Unit

Hz

Hz

ns

ns

ns

ns

ns

ns

s

ns

6. The output word rate, OWR, refers to the frequency at which an audio sample is output from the part.

(A stereo pair is two audio samples.) Therefore, in Master mode, there are always 32 SCK periods in

one audio sample. In Slave mode, exactly 32 SCK periods per audio sample must be provided in most

serial port formats. Therefor, if SCK is 128 x Fs, then SCK must be gated to provide exactly 32 periods

per audio sample.

7. In master mode SCK and FSYNC are outputs. In Slave mode they are inputs. In the CS8411, control

reg. 2 bit 1, MSTR, selects master. In the CS8412, formats 1, 3 and 9 are slaves.

8. The table above assumes data is output on the falling edge and latched on the rising edge. With the

CS8411 the edge is selectable. The table is defined for the CS8411 with control reg. 2 bit 0, SCED, set

to one, and for the CS8412 in formats 2, 3, 5, 6 and 7. For the other formats, the table and figure edges

must be reversed (i.e.. "rising" to "falling" and vice versa).

FSYNC

tsfds

SCK

SDATA

tfss

tsckl tsckh

tssv

MSB

(Mode 1)

FSYNC

tsfds

tfss

tsckl tsckh

SCK

SDATA

tssv

MSB

(Mode 3)

Serial Output Timing - Slave Mode

MCK

tmfd

FSYNC

FSYNC Generated From

Received Data

C, U

tcuvf

FSYNC

tsfdm

SCK

(Modes 2,3,5,6, tssv

7,10,12, and 13)

SCK

(Modes 0,1,4,

8,9, and 11)

SDATA

Serial Output Timing -

Master Mode & C, U Port

DS61F1

5

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