STA304 데이터 시트보기 (PDF) - STMicroelectronics
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STA304 Datasheet PDF : 30 Pages
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STA304
6.0 SAMPLE RATE CONVERTER
The sample rate converter resamples the selected input data source in order to send to the DSP an audio
stream with a fixed frequency of 48 KHz. The following picture show the basic architecture.
Figure 4.
D AT A_I N
LRCK_IN
Interpolation 2 x Fs
FIR x2
Fs
Anti-Alias
FILT
Fs
Interpolation 4xFs or 2xFs
FIR x2
Thresh.
Selector
DRLL RATIO
Sinc 6
Async.
DATA_OUT
48KHz
The selection between X2 Fir interpolation or direct antialiasing Filter on input data is made automatically by the
threshold selector block. If the input sampling frequency (measured by DRLL) is high than the SRC threshold
(see Table 2 section 12.9), the direct antialising filter is selected, otherwise if the input frequency is lower than
the SRC threshold, the X2 FIR filter is added the data path. A 1kHz hysteresis is fixed around the SRC threshold
nominal values of tab. 2 section 12.9, to prevent unstable oscillations. In figure 5 the DRLL lock phase is shown
for 32kHz,44.1kHz, 48kHz and 96kHz input frequency. Note that only after this phase (including the flat part of
the graph) the SRC performances are in spec.
Figure 5. DRLL lock delay
x 104
10
9
8
7
6
5
4
3
2
1
0
0
0.05
0.1
0.15
0.2
0.25
Second
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