HSP50210JI-52 데이터 시트보기 (PDF) - Intersil

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HSP50210JI-52

Digital Costas Loop

Intersil 

HSP50210

Pin Description (Continued)

NAME

TYPE

DESCRIPTION

OEA

I

A Output Enable. This pin is the three-state control pin for the AOUT9-0. When OEA is high, the AOUT9-0 is high

impedance.

OEB

I

B Output Enable. This pin is the three-state control pin for the BOUT9-BOUT0. When OEB is high, the AOUT9-0 is

high impedance.

HI/LO

0

HI/LO. The output of the Input Level Detector is provided on this pin (see “Input Level Detector” on page 6). This

signal can be externally averaged and used to control the gain of an amplifier to close an AGC loop around the A/D

converter. This type of AGC sets the level based on the median value on the input.

CLK

I

System Clock. Asynchronous to the processor interface and serial inputs.

4

FN3652.5

July 2, 2008

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