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HSP50210JC-52 데이터 시트보기 (PDF) - Intersil
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HSP50210JC-52
Digital Costas Loop
Intersil
HSP50210JC-52 Datasheet PDF : 51 Pages
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REGISTER ENABLE RATE
@
= SYNC RATE
*
= TWICE SYMBOL RATE
!
= SYMBOL RATE
BLANK = CLK RATE
HI / LO
MATCHED FILTERING
REG
REG
NCO MIXER
BYPASS
MIXER
R
E
G
R
E
GM
U
RR X
COMPLEX E E
MULTIPLY G G
RR
EE
GG
BYPASS
RRC
M
15 TAP RRC
RR
U
X
@
EE
GG
15 TAP RRC R R
EE
@
GG
REG REG
REG REG
ROOT RAISED COSINE
(RRC)
SIN / COS
ROM
REG
+
REG
CF
REGISTER
FROM CARRIER TRACKING
LOOP FILTER
TO SYMBOL TRACKING
MID AND END
SYMBOL SAMPLES
I I QQ
MID END MID END
FALSE LOCK
RR
L
EE
I
GG
M
I
RR
T
EE
GG
REG
DATA DE-SKEW
DUMP
OQPSK
COMPARE
“0”
M
U
X
R
M
RU
S
H
I
R
E
+
+
DUMP
E
G
@
EX
F
T
G
G
*
*
TWO SAMPLE
M
U
M
“0”
SUMMER
X
U
XR
S
H
+
E
I
G
F
T
@
R
E
+
G
*
INTEGRATE AND DUMP
D
R
E
E
M
U
SOFT
G
X
DECISION
SLICER
D
R
E
E
M
U
G
X
TEST
R R
EE
M
GG
U
RR
X
EE
GG
CARTESIAN TO
POLAR
5
8
I
2
+Q
2
DELAY
REG
M
U
X
TAN
-1
(
QI
)
5
DELAY
8
REG
*
PHASE OUT AT
@
OR
MAG OUT AT
@
OR
!
O
U
T
P
UR
TE
G
SR
EE
L
E
G
C
T
AGC LOOP FILTER
L
R
I
EM
G
I
T
@
OR
!
+
R
E
S
H
I
R
E
GFG
T
HOLD AGC
“0”
M
U
X
AGC ERROR DETECT
AGC THRESHOLD
GAIN
ERROR
-
+
POWER
THRESHOLD
TO
CARRIER
TRACKING
AND
DISCRIMINATOR
UPPER LOWER
GAIN GAIN
LIMIT LIMIT
LOOP GAIN LOOP GAIN
EXPONENT MANTISSA
COMPARE
R
THRESH
E
G
FIGURE 3. MAIN DATA PATH
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