MH8910-1AC 데이터 시트보기 (PDF) - Mitel Networks
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MH8910-1AC Datasheet PDF : 26 Pages
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Preliminary Information
MT8910-1
allocated to the B1 and B2 channels, respectively. In
this mode, the CDSTi and CDSTo streams are not
used. In the dual port mode, the MT8910-1 uses
both the DSTi/DSTo streams as well as the CDSTi/
CDSTo streams to allow the separation of the data
and control. The two B-channels are routed through
the DSTi/DSTo streams and the C- and D-channels
are routed through the CDSTi/CDSTo streams. In
each case, timeslot 0 and 16 will carry the respective
channels (refer to Figure 9). To simplify line card
designs, the MT8910-1 provides a delayed frame
pulse (F0od) to eliminate the need for a channel
assignment circuit. This signal is used to drive
subsequent devices in the daisy chain configuration.
In this type of arrangement, only the first MT8910-1
in the chain will receive the system frame pulse (F0b)
with the following devices receiving its predecessor's
delayed frame pulse. In conjunction with the delayed
frame pulse, the unused timeslots on the ST-BUS
will be placed into a high impedance state to avoid
having contention on the system bus.
Selecting the single port or the dual port mode is
performed using Mode Select 1 (MS1). With MS1=0,
the DSLIC is in the single port mode while MS1=1
places the DSLIC in the dual port mode. Mode
Select 0 (MS0) determines the order of the D- and C-
channels while the DSLIC is operating in the dual
port mode. With MS0 = 0, the C-channel is found
in timeslot 0 and the D-channel is found in timeslot
16. With MS0=1, the D-channel is found in timeslot
0 and the C-channel is found in timeslot 16 (refer to
Table 1).
MS1 MS0
Operating Mode
Dual/Single
DC/CD
0
0
Single
DC
0
1
Single
DC
1
0
Dual
CD
1
1
Dual
DC
Table 1. Truth Table for Mode Select Pins
Control/Status Channels
The Control and Status information between the
DSLIC transceiver and the controlling entity is
carried by the C-channel. The DSLIC has three input
registers; Control Register 1, 2 and 3 (selected
through the CRS0 and CRS1 bits) and four output
registers; Status Register 1 through Status Register
4 (selected through the SRS0 and SRS1 bits in
Control Register 1).
The input C-channel is used to access Control
Registers 1, 2 and 3. Bit 0 and 1 of the C-channel
(CRS0 and CRS1) allows the selection of the desired
Control Register as described following.
CRS1
0
0
0
1
CRS0 Definition
0 Control Register 1
1 Control Register 2
0 Control Register 3
1 Reserved
The C-channel on the ST-BUS must be continuously
written to every frame. If the user accesses a
Control Register, the information in the other Control
Registers is latched. Any input requested through
the Control Registers will be activated on the next
frame boundary.
Control Register 1
Setting CRS0 and CRS1=0 routes the C-channel to
Control Register 1 allowing access to the functions
described in Table 2. These bits are further
described below.
Bits 7 and 6 of Control Register 1, SRS1 & SRS0,
select which status register will be output in the next
ST-BUS frame. The selection of the Status Register
is as follows:
SRS1
0
0
1
1
SRS0
0
1
0
1
Definition
Status Register 1
Status Register 2
Status Register 3
Status Register 4
Bit 5 of Control Register 1, TxSFB, is used to
establish the position of the transmit superframe (LT
mode only). Setting this bit from a logic one to a
logic zero will reset the frame counters on the next
occurrence of the frame pulse establishing the
superframe position. Once the boundaries to the
superframe have been established, the device will
sustain the position of the superframe by allowing
the counters to wrap around. The user can also
elect to set this bit to a logic zero with a periodicity of
12 ms.
Bit 4 of Control Register 1, BSWAP, allows the
multiplexing of the two B-channels transferred over
the digital subscriber line with the B-channels
presented at the system interface. A logic high on
the bit will result in the B1-channel on the system
interface to be transmitted in the B2-channel on the
line port and vice versa. The same principle applies
to the B2-channel at the system interface.
Bit 3 of Control Register 1, CCRC, allows the user to
introduce errors in the CRC bits calculated by the
DSLIC. This allows the user to verify the error
detection protocol used over the M-channel.
9-13
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