XE1205 데이터 시트보기 (PDF) - Semtech Corporation

부품명

상세내역

제조사

XE1205

180 MHz – 1GHz Low-Power, High Link Budget Integrated UHF Transceiver

Semtech Corporation 

XE1205

/RXParam_Disable_bitsync

= ‘0’

RXParam_Pattern

= ‘1’

Q_lim

FSK

I_lim DEMODULATOR

data

BIT

SYNCHRONIZER dclk

PATTERN

MATCHING

Shift reg

8

pattern

write_byte

IRQ_0

/fifoempty

RXParam_RSSI

FIFO

Fifofull

IRQ_1

RSSI

RSSI_irq

8

SPI

DATA

regspidata

MOSI

MISO

SCK

NSS_DATA

.

Figure 8: Receiver chain in buffered mode

If IRQParam_Start_fill is high, FIFO filling is initiated by asserting IRQParam_Start_detect.

Once sixteen bytes have been written to the FIFO the IRQParam_Fifofull signal is asserted. Data should then normally

be read out. If no action is taken the FIFO will overflow and subsequent data will be lost. If this occurs the

IRQParam_Fifooverrun bit is set. The IRQParam_Fifofull signal can be mapped to pin IRQ_1 as an interrupt for a

microcontroller if IRQParam_RX_irq_1 is set to “01” (please refer to section 5.2.2).

To recover from an overflow situation a ‘1’ must be written to IRQParam_Fifooverrun; this clears the contents of the

FIFO, resets all FIFO status flags and re-initiates pattern matching (only when an overrun has occurred).

In order to clear the FIFO in reception, a “1” should be written in IRQParam_start_detect (bit 6 add 6).

Pattern matching can also be re-initiated during a FIFO filling sequence by writing a ‘1’ to IRQParam_Start_detect.

© Semtech 2008

www.semtech.com

15

Share Link: