MC100EP33D(2002) 데이터 시트보기 (PDF) - ON Semiconductor

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MC100EP33D
(Rev.:2002)

3.3V / 5V ECL ÷4 Divider

ON Semiconductor 

MC10EP33, MC100EP33

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0

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fin, INPUT FREQUENCY (MHz)

Figure 3. Input Frequency (fin) versus Output Voltage (VOPP)

Driver

Device

Q

Q

50 W

D

Receiver

Device

D

50 W

V TT

V TT = V CC – 2.0 V

Figure 4. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020 – Termination of ECL Logic Devices.)

Resource Reference of Application Notes

AN1404

AN1405

– ECLinPS Circuit Performance at Non–Standard VIH Levels

– ECL Clock Distribution Techniques

AN1406 – Designing with PECL (ECL at +5.0 V)

AN1504 – Metastability and the ECLinPS Family

AN1568 – Interfacing Between LVDS and ECL

AN1650 – Using Wire–OR Ties in ECLinPS Designs

AN1672 – The ECL Translator Guide

AND8001 – Odd Number Counters Design

AND8002 – Marking and Date Codes

AND8009 – ECLinPS Plus Spice I/O Model Kit

AND8020 – Termination of ECL Logic Devices

For an updated list of Application Notes, please see our website at http://onsemi.com.

http://onsemi.com

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