XRD64L42 데이터 시트보기 (PDF) - Exar Corporation

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XRD64L42

Dual 10-Bit 40MSPS CMOS ADC

Exar Corporation 

XRD64L42

Differential Inputs

The XRD64L42 can be used in either differential or

single-ended input mode. For single-ended inputs, see

the Single-Ended Inputs Section. Differential inputs

reduce system noise by removing noise components

common at both input pins. Figure 4. is a simplified

diagram that is used as a common test circuit with our

XRD64L42/64L44EVAL application board. This circuit

is used to evaluate the dynamic performance of the

XRD64L42 using differential inputs. Pin 15, DIFF

should be held high to select differential inputs.

Auto-Calibration

The XRD64L42 incorporates an auto-calibration circuit

which continuously adjusts and matches the offset and

linearity of each ADC. This auto-calibration circuit is

transparent to the user after the initial 3.4ms calibration

(168,000 initial clock cycles).

Note: To avoid auto-calibration after power down, do not

disable CKIN. CKIN can be slowed down signifi-

cantly to save power without losing calibration.

Input A

Input B

Transformer

22

22

50

Transformer

22

22

50

VINA(+)

VINA(-)

VCMO

VINB(+)

VINB(-)

Figure 5. Common Test Circuit for the

Differential Input Mode

SYNCO, Data Valid Delay and Latency

SYNCO is an output pin provided by the XRD64L42.

Valid data is available on the rising edge of SYNCO,

see Figure 6. The Latency for the XRD64L42 is 17

clock cycles.

CKIN

N

N+1

N+2

Valid Data

SYNCO

N-17

tden=20ns

N-16

N-15

tsynco=2ns (typical)

Figure 6. SYNCO, Data Valid Delay and Latency

for the XRD64L42

Rev. P2.10

11

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