YSS932 데이터 시트보기 (PDF) - Yamaha Corporation

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YSS932

96kHz DIR + Dolby Digital / Pro Logic II / DTS decoder + Sub DSP

Yamaha Corporation 

YSS932

BLOCK DIAGRAM

DIRPCO

DIRPRO

DIRSDO

SDIA

SURENC

KARAOKE

MUTE

CRC

AC3DATA

DTSDATA

NONPCM

ZEROFLG

XI

XO

CPO

SDOA0

SDOA1

SDOA2

SDIB0

SDIB1

SDIB2

SDIB3

VMOD BSMOD

DBL

PLL

Clock for DIR

Block (25MHz)

DIRO Interface

765

DDINSEL

DIR

IPORT5-7

UMOD CMOD

CRC

SDIASEL

SDIA Interface

PLL

Clock for DSP

Block (30MHz)

MainDSP

(AC-3/ProLogicII/DTS decoder)

SDOA Interface

L,R

LS,RS

C,LFE

SDIACKSEL

SDIBSEL

RAMD0-15

CASN

RASN

RAMWEN

RAMOEN

RAMA0-17

OVFB/END

SDIB Interface

OVFB

END

SubDSP

Coefficient /

Program RAM

SDOB Interface

DIRMCK

DIRBCK

DIRWCK

SDBCKI0

SDWCKI0

/SDBCKO

IPORT0-4

/CS

SO

SI

SCK

OPORT0-7

3

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