M65863FP 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC
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M65863FP Datasheet PDF : 61 Pages
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Product Note
April 1998
M65863FP
Dolby Digital Decoder
Pin
No. Pin Name Pins I/O Out Voltage
Description
34 GND
35 VDD5V
36 BCLK
37 LRCK
38 2LRCK
39 2BCLK
40 VDD3V
41 PLLGND
1 O 4mA D5 Bit clock for PCM output
1 O 4mA D5 LR clock for PCM output
1 O 2mA D5 LR clock for 2nd DSP
1 O 2mA D5 Bit clock for 2nd DSP
1-
GND for PLL
42 PVCO
1O
P3.3 Processor clock output for crystal
43 PCLK
1I
P3.3 Processor clock input
44 PLL1
45 PLL2
46 PLL3
47 PLLVCC
48 GND
49 GND
50 GND
51 GND
52 MCLSI[0]
53 MCLSI[1]
54 VDD3V
55 VDD5V
1 I/O
1 I/O
1 I/O
1-
2I
P3.3 VDD for PLL
Selection of audio master clock
D5 ([0:1] = 00 : 512fs, 01 : 384fs, 10 : 256fs, 11 : Reserved)
56 _RST
57 CHIPMOD
58 DECSTAT
59 GND
60 DIRSTAT
61 MCUSEL
62 VDD5V
63 _NC/SS
64 ADR/SO
1I
D5 Reset
1I
D5 Chip mode
1 O 2mA D5 Decode status (Normal : 1, Error : 0)
1 O 2mA D5 (AC-3 : 1, PCM : 0)
1I
D5 MCU I/F Selection (Clocked serial : 0, I2C : 1)
1I
D5
1 O 4mA D5
65 HSDA/SI
66 HSCL/SCK
67 GND
68 GND
1 I/O 4mA D5
1 I/O 4mA D5
Note) D5 : Degital 5V I/O
P3.3 : PLL oscillation I/O
<Audio input interface>
ACLK1
Bit clock input for DIR/ADC input (Line 1).
ADATA1
Data input for DIR/ADC interface (Line 1). Latched at the rising edge of ACLK1.
ALRCK1
LR clock input for DIR/ADC interface (Line 1).
ACLK2
Bit clock input for DIR/ADC input (Line 2).
ADATA2
Data input for DIR/ADC interface (Line 2). Latched at the rising edge of ACLK2.
ALRCK2
LR clock input for DIR/ADC interface (Line 2)
ACLKS
Clock for DEMUX interface.
MITSUBISHI ELECTRIC CORPORATION
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