L9949 데이터 시트보기 (PDF) - STMicroelectronics
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L9949 Datasheet PDF : 20 Pages
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L9949
PIN FUNCTION
N°
Pin
Description
1, 10,
11, 20
GND
Ground:
Reference potential
Important: For the capability of driving the full current at the outputs all pins of GND must be
externally connected !
5, 8, 13,
18
VS Power supply voltage (battery):
For this input a ceramic capacitor as close as possible to GND is recommended.
Important: For the capability of driving the full current at the outputs all pins of VS must be
externally connected !
15
VCC Logic supply voltage:
For this input a ceramic capacitors as close as possible to GND are recommended.
14
CSN Chip Select Not input:
This input is low active and requires CMOS logic levels. The serial data transfer between L9949
and micro controller is enabled by pulling the input CSN to low level. If an input voltage of more
than 9.6V above VCC is applied to CSN pin the L9949 will be switched into a test mode.
6
CLK Serial clock input:
This input controls the internal shift register of the SPI and requires CMOS logic levels.
7
Data In Serial data input:
The input requires CMOS logic levels and receives serial data from the microcontroller. The data
is an 16bit control word and the least significant bit (LSB, bit 0) is transferred first.
17 Data Out Serial data output:
The diagnosis data is available via the SPI and this tristate-output. The output will remain in
tristate, if the chip is not selected by the input CSN (CSN = high)
16
CM Current monitor output:
Depending on the multiplexer bits 12 and 13 of the Input Data register this output sources an
image of the instant current through the corresponding highside driver with a ratio of 1/10000
9
OUT1 Halfbridge-output 1:
The output is built by a highside and a lowside switch, which are internally connected. The
output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic
reverse diode (bulk-drain-diode, highside driver from OUT1 to VS, lowside driver from GND to
OUT1). This output is overcurrent and open load protected.
12
→ OUT2 Halfbridge-output 2:
see OUT1 (pin 9)
2
OUT3 Halfbridge-output 3:
The output is built by a highside and a lowside switch, which are internally connected. The
output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic
reverse diode (bulk-drain-diode, highside driver from OUT3 to VS, lowside driver from GND to
OUT3). This output is overcurrent and open load protected.
3
→ OUT4 Halfbridge-output 4:
see OUT3 (pin 2)
4
→ OUT5 Halfbridge-output 5:
see OUT3 (pin 2)
19
OUT6 Highside-driver-output 6:
The output is built by a highside switch and can be used only for a resistive load, because the
internal reverse diode from GND to OUT6 is missing. This highside switch is a power DMOS
transistor with an internal parasitic reverse diode from OUT6 to VS (bulk-drain-diode). The output
is overcurrent and open load protected.
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