FM-1288-GE-400B 데이터 시트보기 (PDF) - Unspecified

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FM-1288-GE-400B

High Performance Voice Processor for Automotive Handsfree

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FIGURES

Figure 1: LQFP Pin Configuration -Top View..........................................................................................9

Figure 2: IC Hardware Block Diagram.................................................................................................13

Figure 3: Example Bluetooth Application Block Diagrams .....................................................................14

Figure 4: FM-1288 as an example Stand-alone Minimal System............................................................15

Figure 5: Example UART Command Protocol .......................................................................................22

Figure 6: UART Data Transfers (TX and RX) .......................................................................................22

Figure 7: SHI Data Transfer Command Protocol ..................................................................................23

Figure 8: SHI Command Sequence.....................................................................................................24

Figure 9: IIS Falling Edge Latch, LRCK High for Left Channel, 1 Cycle Delay .........................................27

Figure 10: IIS Falling Edge Latch, LRCK High for Left Channel, 0 Cycle Delay .......................................28

Figure 11: IIS Falling Edge Latch, LRCK High for Right Channel, 1 Cycle Delay .....................................28

Figure 12: IIS Falling Edge Latch, LRCK High for Right Channel, 0 Cycle Delay .....................................29

Figure 13: IIS Rising Edge Latch, LRCK High for Left Channel, 1 Cycle Delay ........................................29

Figure 14: IIS Rising Edge Latch, LRCK High for Left Channel, 0 Cycle Delay ........................................30

Figure 15: IIS Rising Edge Latch, LRCK High for Right Channel, 1 Cycle Delay ......................................30

Figure 16: IIS Rising Edge Latch, LRCK High for Right Channel, 0 Cycle Delay ......................................31

Figure 17: Analog-to-Digital Converter Block Diagram .........................................................................32

Figure 18: Digital-to-Analog Converter Block Diagram .........................................................................33

Figure 19: State Transition Diagram ...................................................................................................35

Figure 20: Accessing FM1288.............................................................................................................39

Figure 21: Command Entry Data Pattern ............................................................................................39

Figure 22: Timing Chart: Power-Up Initialization .................................................................................49

Figure 25: Master Clock (MCLK) Timing ..............................................................................................50

Figure 26: SHI Timing .......................................................................................................................50

Figure 27: 48-pin LQFP Package Drawing and Dimensions...................................................................54

Figure 28: 48-pin LQFP Package Side View .........................................................................................55

Figure 29: 48-pin LQFP Package on FM-1288......................................................................................56

Figure 30: External Crystal/Oscillator as Clock Source .........................................................................58

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