MC100LVEL13(2016) 데이터 시트보기 (PDF) - ON Semiconductor
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MC100LVEL13 Datasheet PDF : 6 Pages
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MC100LVEL13
Q1a Q1a Q2a Q2a VCC Q2b Q2b Q1b Q1b VEE
20 19 18 17 16 15 14 13 12 11
Table 1. PIN DESCRIPTION
PIN
FUNCTION
Qna, Qna
Qnb, Qnb
CLKn, CLKn
VCC
VEE
ECL Differential Clock Outputs
ECL Differential Clock Outputs
ECL Differential Clock Inputs
Positive Supply
Negative Supply
1 2 3 4 5 6 7 8 9 10
Q0a Q0a VCC CLKa CLKa CLKb CLKb VCC Q0b Q0b
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. Logic Diagram and Pinout: 20-Lead SOIC
(Top View)
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC PECL Mode Power Supply
VEE
NECL Mode Power Supply
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VEE = 0 V
VCC = 0 V
VI ≤ VCC
VI ≥ VEE
8 to 0
V
−8 to 0
V
6 to 0
V
−6 to 0
V
Iout
Output Current
Continuous
Surge
50
mA
100
TA
Operating Temperature Range
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−20 WB
SOIC−20 WB
−40 to +85
−65 to +150
90
60
°C
°C
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
SOIC−20 WB
30 to 35
°C/W
Tsol
Wave Solder (Pb-Free)
< 2 to 3 sec @ 260°C
265
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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