29F128G08CEAAA 데이터 시트보기 (PDF) - Micron Technology

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29F128G08CEAAA

NAND Flash Memory

Micron Technology 

Micron Confidential and Proprietary

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

List of Figures

Figure 1: Part Numbering ................................................................................................................................ 2

Figure 2: 48-Pin TSOP Type 1 (Top View) ....................................................................................................... 11

Figure 3: 52-Pad LGA (Top View) ................................................................................................................... 12

Figure 4: 100-Ball BGA (Ball-Down, Top View) ................................................................................................ 13

Figure 5: 48-Pin TSOP – Type 1 CPL (Package Code: WP) ................................................................................ 14

Figure 6: 52-Pad VLGA .................................................................................................................................. 15

Figure 7: 100-Ball VBGA – 12mm x 18mm (Package Code: H1) ......................................................................... 16

Figure 8: 100-Ball TBGA – 12mm x 18mm (Package Code: H2) ......................................................................... 17

Figure 9: 100-Ball LBGA – 12mm x 18mm (Package Code: H3) ......................................................................... 18

Figure 10: NAND Flash Die (LUN) Functional Block Diagram ......................................................................... 19

Figure 11: Device Organization for Single-Die Package (TSOP/BGA) ............................................................... 20

Figure 12: Device Organization for Two-Die Package (TSOP) .......................................................................... 21

Figure 13: Device Organization for Two-Die Package (BGA/LGA) .................................................................... 22

Figure 14: Device Organization for Four-Die Package (TSOP) .......................................................................... 23

Figure 15: Device Organization for Four-Die Package with CE# and CE2# (BGA/LGA) ...................................... 24

Figure 16: Device Organization for Four-Die Package with CE#, CE2#, CE3#, and CE4# (BGA/LGA) .................. 25

Figure 17: Device Organization for Eight-Die Package (BGA/LGA) ................................................................... 26

Figure 18: Array Organization per Logical Unit (LUN) ..................................................................................... 27

Figure 19: Asynchronous Command Latch Cycle ............................................................................................ 29

Figure 20: Asynchronous Address Latch Cycle ................................................................................................ 30

Figure 21: Asynchronous Data Input Cycles ................................................................................................... 31

Figure 22: Asynchronous Data Output Cycles ................................................................................................. 32

Figure 23: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 33

Figure 24: READ/BUSY# Open Drain ............................................................................................................. 34

Figure 25: tFall and tRise (VCCQ = 2.7-3.6V) ...................................................................................................... 35

Figure 26: tFall and tRise (VCCQ = 1.7-1.95V) .................................................................................................... 35

Figure 27: IOL vs Rp (VCCQ = 2.7-3.6V) ............................................................................................................ 36

Figure 28: IOL vs Rp (VCCQ = 1.7-1.95V) .......................................................................................................... 36

Figure 29: TC vs Rp ........................................................................................................................................ 37

Figure 30: Synchronous Bus Idle/Driving Behavior ......................................................................................... 40

Figure 31: Synchronous Command Cycle ....................................................................................................... 41

Figure 32: Synchronous Address Cycle ........................................................................................................... 42

Figure 33: Synchronous DDR Data Input Cycles ............................................................................................. 43

Figure 34: Synchronous DDR Data Output Cycles ........................................................................................... 45

Figure 35: R/B# Power-On Behavior ............................................................................................................... 46

Figure 36: Activating the Synchronous Interface ............................................................................................. 48

Figure 37: RESET (FFh) Operation ................................................................................................................. 51

Figure 38: SYNCHRONOUS RESET (FCh) Operation ....................................................................................... 52

Figure 39: RESET LUN (FAh) Operation ......................................................................................................... 53

Figure 40: READ ID (90h) with 00h Address Operation .................................................................................... 54

Figure 41: READ ID (90h) with 20h Address Operation .................................................................................... 54

Figure 42: SET FEATURES (EFh) Operation .................................................................................................... 57

Figure 43: GET FEATURES (EEh) Operation ................................................................................................... 57

Figure 44: READ PARAMETER (ECh) Operation .............................................................................................. 61

Figure 45: READ UNIQUE ID (EDh) Operation ............................................................................................... 72

Figure 46: READ STATUS (70h) Operation ...................................................................................................... 75

Figure 47: READ STATUS ENHANCED (78h) Operation .................................................................................. 75

Figure 48: CHANGE READ COLUMN (05h-E0h) Operation ............................................................................. 76

Figure 49: CHANGE READ COLUMN ENHANCED (06h-E0h) Operation ......................................................... 77

Figure 50: CHANGE WRITE COLUMN (85h) Operation ................................................................................... 78

PDF: 09005aef83d2277a

Rev. A 11/09 EN

6

Micron Technology, Inc. reserves the right to change products or specifications without notice.

©2009 Micron Technology, Inc. All rights reserved.

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