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74LV153

Dual 4-input multiplexer

Philips Electronics 

Philips Semiconductors

Dual 4-input multiplexer

Product specification

74LV153

FEATURES

• Optimized for low voltage applications: 1.0 to 3.6 V

• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

• Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,

Tamb = 25°C

• Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V,

Tamb = 25°C

• Non-inverting outputs

• Separate enable for each output

• Common select inputs

• Permits multiplexing from n lines to 1 line

• Enable line provided for cascading (n lines to 1 line)

• Output capability: standard

• ICC category: MSI

DESCRIPTION

The 74LV153 is a low-voltage CMOS device that is pin and function

compatible with 74HC/HCT153.

The 74LV153 is a dual 4-input multiplexer which selects 2 bits of

data from up to four sources selected by common data select inputs

(S0, S1). The two 4-input multiplexer circuits have individual active

LOW output enable inputs (1E, 2E) which can be used to strobe the

outputs independently. The outputs (1Y, 2Y) are forced LOW when

the corresponding output enable inputs are HIGH. The 74LV153 is

the logic implementation of a 2-pole, 4-position switch, where the

position of the switch, is determined by the logic levels applied to S0

and S1. The logic equations for the outputs are:

1Y=1E.(1l0.S1.S0+1l1.S1.S0+1l2.S1.S0+1l3.S1.S0)

2Y=2E.(2l0.S1.S0+2l1.S1.S0+2l2.S1.S0+2l3.S1.S0)

The 74LV153 can be used to move data to a common output bus

from a group of registers. The state of the select inputs would

determine the particular register from which the data came. An

alternative application is a function generator. The device can

generate two functions or three variables. This is useful for

implementing highly irregular random logic.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns

SYMBOL

PARAMETER

CONDITIONS

tPHL/tPLH

Propagation delay

1ln, 2ln to nY

Sn to nY

nE to nY

CL = 15 pF;

VCC = 3.3 V

CI

Input capacitance

CPD

Power dissipation capacitance per gate VI = GND to VCC1

NOTE:

1. CPD is used to determine the dynamic power dissipation (PD in µW)

PD = CPD × VCC2 × fi )ȍ (CL × VCC2 × fo) where:

fi = input frequency in MHz; CL = output load capacitance in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

ȍ (CL × VCC2 × fo) = sum of the outputs.

TYPICAL

14

14

10

3.5

30

ORDERING INFORMATION

PACKAGES

16-Pin Plastic DIL

16-Pin Plastic SO

16-Pin Plastic SSOP Type II

16-Pin Plastic TSSOP Type I

TEMPERATURE RANGE OUTSIDE NORTH AMERICA

–40°C to +125°C

74LV153 N

–40°C to +125°C

74LV153 D

–40°C to +125°C

74LV153 DB

–40°C to +125°C

74LV153 PW

NORTH AMERICA

74LV153 N

74LV153 D

74LV153 DB

74LV153PW DH

UNIT

ns

pF

pF

PKG. DWG. #

SOT38-4

SOT109-1

SOT338-1

SOT403-1

1998 Apr 28

2

853–1921 19309

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