AT24C01D-CUM-T 데이터 시트보기 (PDF) - Unspecified
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AT24C01D-CUM-T Datasheet PDF : 26 Pages
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1. Pin Descriptions and Pinouts
Table 1-1. Pin Descriptions
Pin
Pin
Number Symbol Pin Name and Functional Description
Asserted
State
Device Address Inputs: The A0, A1, and A2 pins are used to select the
hardware device address and correspond to the seventh, sixth, and fifth
1, 2, 3 A0, A1, A2 bit of the I2C seven bit slave address. These pins can be directly
—
connected to VCC or GND, allowing up to eight devices on the same bus.
Refer to Note 1 for behavior of the pin when not connected.
Ground: The ground reference for the power supply. GND should be
4
GND
—
connected to the system ground.
Serial Data: The SDA pin is an open-drain bidirectional input/output pin
used to serially transfer data to and from the device.
5
SDA The SDA pin must be pulled-high using an external pull-up resistor (not to
—
exceed 10K in value) and may be wire-ORed with any number of other
open-drain or open-collector pins from other devices on the same bus.
Serial Clock: The SCL pin is used to provide a clock to the device and to
control the flow of data to and from the device. Command and input data
present on the SDA pin is always latched in on the rising edge of SCL,
6
SCL while output data on the SDA pin is clocked out on the falling edge of SCL.
—
The SCL pin must either be forced high when the serial bus is idle or
pulled-high using an external pull-up resistor.
Write Protect: Connecting the WP pin to GND will ensure normal write
operations.When the WP pin is connected to VCC, all write operations to
7
WP
the memory are inhibited.
High
Refer to Note 1 for behavior of the pin when not connected.
Device Power Supply: The VCC pin is used to supply the source voltage
8
VCC to the device. Operations at invalid VCC voltages may produce spurious
—
results and should not be attempted.
Pin
Type
Input
Power
Input/
Output
Input
Input
Power
Note:
1. If the A0, A1, A2, or WP pins are not driven, they are internally pulled down to GND. In order to operate in a wide
variety of application environments, the pull-down mechanism is intentionally designed to be somewhat strong.
Once these pins are biased above the CMOS input buffer’s trip point (~0.5 x VCC), the pull-down mechanism
disengages. Atmel recommends connecting these pins to a known state whenever possible.
Note:
8-lead SOIC
A0
A1
A2
GND
1
8
2
7
3
6
4
5
Top View
VCC
WP
SCL
SDA
8-lead PDIP
8-lead TSSOP
A0
1
A1
2
A2
GND
3
4
8
VCC
7
WP
6
SCL
5
SDA
Top View
(1)
5-lead SOT23
8-pad UDFN
A0 1
A1 2
A2 3
GND 4
8 VCC
7 WP
6 SCL
5 SDA
Top View
8-ball VFBGA
A0 1
A1 2
A2 3
GND 4
8 VCC
7 WP
6 SCL
5 SDA
Top View
SCL
15
WP
GND 2
SDA
34
VCC
Top View
A0 1
A1 2
A2 3
GND 4
8 VCC
7 WP
6 SCL
5 SDA
Top View
Note: Package drawings are not to scale.
1. Refer to Section 4.1, “Device Addressing” on page 7 for details addressing the SOT23 version of the device.
2
AT24C01D and AT24C02D [DATASHEET]
Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015
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