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24AA04-E/OTG 데이터 시트보기 (PDF) - Unspecified

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24AA04-E/OTG
ETC
Unspecified ETC
24AA04-E/OTG Datasheet PDF : 26 Pages
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24AA04/24LC04B
4K I2CSerial EEPROM
Device Selection Table
Part
Number
Vcc
Range
Max Clock
Frequency
24AA04
1.8-5.5
400 kHz(1)
24LC04B 2.5-5.5
400 kHz
Note 1: 100 kHz for VCC <2.5V
Temp
Ranges
I
I, E
Features:
• Single supply with operation down to 1.8V
• Low-power CMOS technology:
- 1 mA active current, typical
- 1 μA standby current, typical (I-temp)
• Organized as 2 blocks of 256 bytes (2 x 256 x 8)
• 2-wire serial interface bus, I2C™ compatible
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (24AA04) and 400 kHz (24LC04B)
compatibility
• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 16 bytes
• Hardware write-protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 erase/write cycles
• Data retention > 200 years
• 8-lead PDIP, SOIC, TSSOP, DFN and MSOP
packages
• 5-lead SOT-23 package
• Pb-free finish available
• Available for extended temperature ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Description:
The Microchip Technology Inc. 24AA04/24LC04B
(24XX04*) is a 4 Kbit Electrically Erasable PROM. The
device is organized as two blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.8V, with standby
and active currents of only 1 μA and 1 mA,
respectively. The 24XX04 also has a page write
capability for up to 16 bytes of data. The 24XX04 is
available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, 2x3 DFN and MSOP packages and is
also available in the 5-lead SOT-23 package.
Package Types
PDIP, MSOP
SOIC, TSSOP
A0 1
A1 2
A2 3
VSS 4
8 VCC A0 1
7 WP A1 2
6 SCL A2 3
5 SDA VSS 4
8 VCC
7 WP
6 SCL
5 SDA
SOT-23-5
DFN
SCL 1
Vss 2
SDA 3
5 WP
4 Vcc
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
Note:
Pins A0, A1 and A2 are not used by the 24XX04. (No
internal connections).
Block Diagram
WP
HV
Generator
I/O
Control
Logic
I/O
SCL
SDA
VCC
VSS
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Latches
YDEC
Sense Amp.
R/W Control
© 2005 Microchip Technology Inc.
DS21708D-page 1

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