74HCT4053D-Q100 데이터 시트보기 (PDF) - NXP Semiconductors.
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74HCT4053D-Q100 Datasheet PDF : 30 Pages
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Nexperia
74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
from
logic
Fig 4. Schematic diagram (one switch)
6. Pinning information
6.1 Pinning
74HC4053-Q100
74HCT4053-Q100
2Y1 1
2Y0 2
3Y1 3
3Z 4
3Y0 5
E6
VEE 7
GND 8
16 VCC
15 2Z
14 1Z
13 1Y1
12 1Y0
11 S1
10 S2
9 S3
aaa-003164
Fig 5. Pin configuration SO16 and TSSOP16
VCC
VEE
Y
VCC
VEE
VCC
VCC
VEE
Z
001aad544
74HC4053-Q100
74HCT4053-Q100
terminal 1
index area
2Y0 2
3Y1 3
3Z 4
3Y0 5
E6
VEE 7
VCC(1)
15 2Z
14 1Z
13 1Y1
12 1Y0
11 S1
10 S2
aaa-003165
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to VCC.
Fig 6. Pin configuration DHVQFN16
74HC_HCT4053_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 November 2012
© Nexperia B.V. 2017. All rights reserved
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