74LVC543A 데이터 시트보기 (PDF) - NXP Semiconductors.
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74LVC543A Datasheet PDF : 21 Pages
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NXP Semiconductors
74LVC543A
Octal D-type registered transceiver; 3-state
5. Pinning information
5.1 Pinning
74LVC543A
LEBA 1
OEBA 2
A0 3
A1 4
A2 5
A3 6
A4 7
A5 8
A6 9
A7 10
EAB 11
GND 12
24 VCC
23 EBA
22 B0
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 LEAB
13 OEAB
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Fig 4. Pin configuration for SO24 and (T)SSOP24
74LVC543A
terminal 1
index area
OEBA 2
A0 3
A1 4
A2 5
A3 6
A4 7
A5 8
A6 9
A7 10
EAB 11
GND(1)
23 EBA
22 B0
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 LEAB
001aaa340
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration for DHVQFN24
5.2 Pin description
Table 2.
Symbol
LEBA
LEAB
OEBA
OEAB
EBA
EAB
A[0:7]
B[0:7]
GND
VCC
Pin description
Pin
1
14
2
13
23
11
3, 4, 5, 6, 7, 8, 9, 10
22, 21, 20, 19, 18, 17, 16, 15
12
24
Description
B to A latch enable input (active LOW)
A to B latch enable input (active LOW)
B to A output enable input (active LOW)
A to B output enable input (active LOW)
B to A enable input (active LOW)
A to B enable input (active LOW)
A data input or output
B data output or input
ground (0 V)
supply voltage
74LVC543A_8
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 18 December 2012
© NXP B.V. 2012. All rights reserved.
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