MC10E1652L 데이터 시트보기 (PDF) - Motorola => Freescale

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MC10E1652L

Dual ECL Output Comparator With Latch

Motorola => Freescale 

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Dual ECL Output Comparator

With Latch

The MC10E1652 is functionally and pin-for-pin compatible with the

MC10E1651 and thus the MC1651 in the MECL III™ family, but is

fabricated using Motorola’s advanced MOSAIC III™ process and is output

compatible with 10H logic devices. In addition, the device is available in

both a 16-pin DIP and a 20-pin surface mount package. However, the

MC10E1652 provides user programmable hysteresis.

The latch enable (LENa and LENb) input pins operate from standard

ECL 10H™ logic levels. When the latch enable is at a logic high level the

MC10E1652 acts as a comparator, hence Q will be at a logic high level if

V1 > V2 (V1 is more positive than V2). Q is the complement of Q. When

the latch enable input goes to a low logic level, the outputs are latched in

their present state, providing the latch enable setup and hold time

constraints are met. The level of input hysteresis is controlled by applying

a bias voltage to the HYS pin.

• Typical 3.0 dB Bandwidth > 1.0 GHz

• Typical V to Q Propagation Delay of 775 ps

• Typical Output Rise/Fall of 350 ps

• Common Mode Range –2.0 V to +3.0 V

• Individual Latch Enables

• Differential Outputs

• Programmable Input Hysteresis

MC10E1652

DUAL ECL OUTPUT

COMPARATOR

WITH LATCH

FN SUFFIX

PLASTIC PACKAGE

CASE 775-02

V1a

V2a

LENa

HYS

V1b

V2b

LENb

12/93

© Motorola, Inc. 1996

LOGIC DIAGRAM

Qa

Qa

Qb

Qb

VEE = –5.2 V

VCC = +5.0 V

2–1

L SUFFIX

CERAMIC PACKAGE

CASE 620-10

FUNCTION TABLE

LEN

H

H

L

V1, V2

V1 > V2

V1 < V2

X

Function

H

L

Latched

REV 1

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