AD5721R 데이터 시트보기 (PDF) - Analog Devices
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AD5721R Datasheet PDF : 36 Pages
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Data Sheet
AD5761R/AD5721R
TIMING CHARACTERISTICS
DVCC = 1.7 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
t11
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
Limit at TMIN, TMAX
20
10
10
15
10
20
5
5
10
20
20
9
7.5
20
200
10
40
50
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs typ
µs typ
ns min
ns typ
ns min
ns max
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge time
Minimum SYNC high time (write mode)
Data setup time
Data hold time
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
DAC output settling time, 20 V step to 1 LSB at 16-bit resolution (see Table 2)
DAC output settling time, 10 V step to 1 LSB at 16-bit resolution
CLEAR pulse width low
CLEAR pulse activation time
SYNC rising edge to SCLK falling edge
SCLK rising edge to SDO valid (CL_SDO2 = 15 pF)
Minimum SYNC high time (readback/daisy-chain mode)
1 Maximum SCLK frequency is 50 MHz for write mode and 33 MHz for readback mode.
2 CL_SDO is the capacitive load on the SDO output.
TIMING DIAGRAMS
t1
SCLK
SYNC
SDI
LDAC
VOUT
VOUT
1
2
t6
t3
t4
t8
t7
DB23
t9
24
t2
t5
DB0
t11
t10
t12
t12
CLEAR
t13
t14
VOUT
Figure 2. Serial Interface Timing Diagram
Rev. C | Page 7 of 36
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