CY7C1061DV18-15BV1XI 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1061DV18-15BV1XI Datasheet PDF : 18 Pages
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CY7C1061DV18
AC Switching Characteristics
Over the Operating Range
Parameter [7]
Description
Read Cycle
tpower
VCC(typical) to the first access [8]
tRC
Read cycle time
tAA
Address to data valid
tOHA
Data hold from address change
tACE
CE1 LOW/CE2 HIGH to data valid
tDOE
OE LOW to data valid
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
OE LOW to Low Z
OE HIGH to High Z [9]
CE1 LOW/CE2 HIGH to Low Z [9]
CE1 HIGH/CE2 LOW to High Z [9]
CE1 LOW/CE2 HIGH to Power-up [10]
CE1 HIGH/CE2 LOW to Power-down [10]
tDBE
Byte Enable to data valid
tLZBE
Byte Enable to Low Z
tHZBE
Byte Disable to High Z
Write Cycle [11, 12]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
tBW
Write cycle time
CE1 LOW/CE2 HIGH to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE HIGH to Low Z[13]
WE LOW to High Z[13]
Byte enable to end of write
-15
Unit
Min
Max
150
–
s
15
–
ns
–
15
ns
3
–
ns
–
15
ns
–
7
ns
1
–
ns
–
7
ns
3
–
ns
–
7
ns
0
–
ns
–
15
ns
–
7
ns
1
–
ns
–
7
ns
15
–
ns
10
–
ns
10
–
ns
0
–
ns
0
–
ns
10
–
ns
7
–
ns
0
–
ns
3
–
ns
–
7
ns
10
–
ns
Notes
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 0.9 V, input pulse levels of 0 to 1.8 V. Test conditions for the Read cycle use
output loading shown in part a) of the Figure 3, unless specified otherwise.
8. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
9. stHteZaOdEy, -tsHtZaCteE,vtoHlZtaWgEe,.tHZBE, and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 3. Transition is measured 200 mV from
10. These parameters are guaranteed by design and are not tested.
11.
The internal Write
be LOW to initiate
atimWeriotef,thaendmtehme otrraynissitdioenfinoef danbyyothf tehoevseerslaigpnoaflsCcEa1nLtOerWmi(nCaEte2tHheIGWHr)itaen. dThWeEinLpOutWd.aCtahsipete-unpabalneds
must be active and WE and byte
hold timing should be referenced
enables must
to the leading
edge of the signal that terminates the Write.
12. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
13. tsHteZaOdEy, -tsHtZaCteE,vtoHlZtaWgEe,.tHZBE, and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 3. Transition is measured 200 mV from
Document Number: 001-08350 Rev. *I
Page 8 of 18
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