Schematic diagram
1
Schematic diagram
TSA1203
Figure 1. TSA1203 block diagram
+2.5V/3.3V
CLK SELECT OEB
VCCBE
VINI
VINBI
VINCMI
VREFPI
VREFMI
IPOL
VREFPQ
VREFMQ
VINCMQ
VINQ
VINBQ
AD 12
I channel
common mode
REF I
Polar.
REF Q
common mode
AD 12
Q channel
Timing
12
M 12
12 D0
U
Buffers
TO
X
D11
12
GND
GNDBE
Figure 2. Timing diagram
Simultaneous sampling on
I/Q channels
N+4
N+3
I
N+2
N-1
N+1
N
Q
N+5
N+6
N+12
N+7
N+11
N+8
N+10
N+9
N+13
CLK
SELECT
Tpd I + Tod
Tod
CLOCK AND SELECT CONNECTED TOGETHER
OEB
DATA
OUTPUT
sample N-9
I channel
sample N-8
I channel
sample N-6
Q channel
sample N-7
Q channel
sample N sample N+1 sample N+2
Q channel Q channel Q channel
sample N+1 sample N+2 sample N+3
I channel I channel I channel
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