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UDA1343TT

Economy audio CODEC with features

Philips Electronics 

Philips Semiconductors

Economy audio CODEC with features

Preliminary specification

UDA1343TT

handbook, halfpage

VSSA(ADC) 1

28 Vref(D)

VDDA(ADC) 2

27 VSSO

VINL 3

26 VOUTL

Vref(A) 4

25 VDDO

VINR 5

24 VOUTR

VADCN 6

23 VDDA(DAC)

VADCP 7

22 VSSA(DAC)

UDA1343TT

TEST1 8

21 TEST2

OVERFL 9

VDDD 10

VSSD 11

SYSCLK 12

20 RESET

19 DATAI

18 DATAO

17 WS

L3MODE 13

16 BCK

L3CLOCK 14

15 L3DATA

MGL887

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION

The UDA1343TT accommodates slave mode only, this

means that in all applications the system devices must

provide the system clock and the serial audio clock

signals.

The system clock must be locked in frequency to the digital

interface input signals.

The BCK clock can be up to 128fs, or in other words the

BCK frequency fBCK is 128 times the Word Select (WS)

frequency fWS or less: fBCK = < 128 × fWS.

Important: the WS edge MUST fall on the negative edge

of the BCK at all times for correct operation of the digital

I/O data interface.

Note: the sampling frequency range is from 8 to 110 kHz,

however for the 512fs clock mode the sampling range is

from 8 to 55 kHz.

Reset

Pin 20 is a reset pin (active HIGH), which resets the

internal digital core of the IC and also resets all feature

values of the L3 interface to their default settings as given

in Tables 8 and 9.

Since the RESET pin is a pull-down pad with

Schmitt-trigger, a Power-On Reset (POR) function can be

made by connecting this pin to the digital power supply via

a capacitor.

Note: care must be taken that during the HIGH period of

the reset signal it is best to have at least 8 SYSCLK clock

cycles to properly reset the device.

Analog-to-Digital Converter (ADC)

The stereo ADC of the UDA1343TT consists of two

5th-order Sigma-Delta modulators. They have a modified

Ritchie-coder architecture in a differential switched

capacitor implementation. The oversampling ratio is 64.

Analog front-end

The analog front-end is equipped with a Programmable

Gain Amplifier (PGA) which can be controlled via the L3

interface. The control range is from 0 dB to 24 dB gain in

3 dB steps independant for left and right.

In applications in which a 2 V (RMS) input signal is used,

a 12 kΩ resistor must be connected in series with the input

of the ADC. This makes a voltage divider with the internal

ADC resistor and makes sure only 1 V (RMS) maximum is

input to the IC. Using this application for a 2 V (RMS) input

signal, the switch must be set to 0 dB. When a 1 V (RMS)

input signal is input to the ADC in the same application, the

gain switch of the PGA must be set to 6 dB via the L3

interface.

An overview of the maximum input voltages allowed

against the presence of an external resistor and the setting

of the gain switch is given in Table 1.

Table 1 Application modes using input gain stage

RESISTOR

(12 kΩ)

Present

Present

Absent

Absent

PGA GAIN

0 dB

6 dB

0 dB

6 dB

MAXIMUM INPUT

VOLTAGE

2 V (RMS)

1 V (RMS)

1 V (RMS)

0.5 V (RMS)

2000 Jan 12

7

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