74LVC125A 데이터 시트보기 (PDF) - NXP Semiconductors.
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74LVC125A Datasheet PDF : 16 Pages
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NXP Semiconductors
5. Pinning information
5.1 Pinning
74LVC125A
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
1OE 1
1A 2
1Y 3
2OE 4
2A 5
2Y 6
GND 7
14 VCC
13 4OE
12 4A
125
11 4Y
10 3OE
9 3A
8 3Y
001aad045
Fig 4. Pin configuration for SO14 and (T)SSOP14
terminal 1
index area
1A 2
1Y 3
2OE 4
2A 5
2Y 6
125
GND(1)
13 4OE
12 4A
11 4Y
10 3OE
9 3A
001aad046
Transparent top view
(1) This is not a supply pin. The substrate is attached to
this pad using conductive die attach material. There
is no electrical or mechanical requirement to solder
this pad. However, if it is soldered, the solder land
should remain floating or be connected to GND.
Fig 5. Pin configuration for DHVQFN14
5.2 Pin description
Table 2. Pin description
Symbol
Pin
1OE, 2OE, 3OE, 4OE 1, 4, 10, 13
1A, 2A, 3A, 4A
2, 5, 9, 12
1Y, 2Y, 3Y, 4Y
3, 6, 8, 11
GND
7
VCC
14
Description
data enable input (active LOW)
data input
data output
ground (0 V)
supply voltage
6. Functional description
Table 3. Function selection[1]
Inputs
nOE
nA
L
L
L
H
H
X
Output
nY
L
H
Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state
74LVC125A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 11 April 2013
© NXP B.V. 2013. All rights reserved.
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