A49LF004 데이터 시트보기 (PDF) - AMIC Technology
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A49LF004 Datasheet PDF : 32 Pages
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A49LF004
Table 6: Lock Register Bit Definition
Data
00h
01h
02h
03h
04h
05h
06h
07h
Reserved
Bit 7:3
00000
00000
00000
00000
00000
00000
00000
00000
Read-Lock
Bit 2
0
0
0
0
1
1
1
1
Lock-Down
Bit 1
0
0
1
1
0
0
1
1
Write-Lock
Bit 0
Function
0
Full Access.
1
Write locked. Default state at power-up.
0
Locked open (full access locked down).
1
Write-locked down.
0
Read locked.
1
Read and Write locked.
0
Read-locked down
1
Read- and Write-locked down
Data
7:3
2
1
0
Function
Reserved
Read-Lock
1 = Prevents read operations in the block where set
0 = Normal operation for reads in the block where clear. This is the default state.
Lock-Down
1 = Prevents further set or clear operations to the Write-Lock and Read-Lock bits. Lock-Down only can be set
but not clear. The block will remain lock-down until reset (with RST# or INIT# being Low), or until the device
is power-on reset.
0 = Normal operation for Write-Lock and Read-Lock bit altering in the block where clear. This is the default state.
Write-Lock
1 = Prevents program or erase operations in the block where set. This is the default state.
0 = Normal operation for programming and erase in the block where clear.
ADDRESS/ADDRESS MULTIPLEXED (A/A
MUX) MODE
Device Operation
Commands are used to initiate the memory operation
functions of the device. The data portion of the software
command sequence is latched on the rising edge of WE#.
During the software command sequence the row address is
latched on the falling edge of R/C# and the column address
is latched on the rising edge of R/C#. Refer to Table 7 and
Table 8 for operation modes and the command sequence.
Read
The Read operation of the A49LF004 device is controlled by
OE#. OE# is the output control and is used to gate data from
the output pins. Refer to the Read cycle timing diagram,
Figure 10 for further details.
Reset
A VIL on RST# pin initiates a device reset.
Byte-Program Operation
The A49LF004 device is programmed on a byte-by-byte
basis. Before programming, one must ensure that the block,
in which the byte which is being programmed exists, is fully
erased. The Byte-Program operation is initiated by executing
a four-byte command load sequence for Software Data
Protection with address and data in the last byte sequence.
During the Byte-Program operation, the row address (A10-
A0) is latched on the falling edge of R/C# and the column
Address (A21-A11) is latched on the rising edge of R/C#.
The data bus is latched in the rising edge of WE#. See
Figure 11 for Program operation timing diagram, Figure 14
for timing waveforms, and Figure 19 for its flowchart. During
the Program operation, the only valid reads are Data#
Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
commands written during the internal Program operation will
be ignored.
PRELIMINARY (November, 2003, Version 0.0)
10
AMIC Technology, Corp.
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