AD7224 데이터 시트보기 (PDF) - Analog Devices

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AD7224

LC2MOS 8-Bit DAC with Output Amplifiers

Analog Devices 

AD7224

BIPOLAR OUTPUT OPERATION

The AD7224 can be configured to provide bipolar output op-

eration using one external amplifier and two resistors. Figure 6

shows a circuit used to implement offset binary coding. In this

case

( ) ( ) VO

=

1 +

R2

R1



•

D

V REF

– 

R2

R1



•

V REF

With R1 = R2

VO = (2 D – 1) • VREF

where D is a fractional representation of the digital word in

the DAC register.

Mismatch between R1 and R2 causes gain and offset errors;

therefore, these resistors must match and track over tempera-

ture. Once again, the AD7224 can be operated in single supply

or from positive/negative supplies. Table III shows the digital

code versus output voltage relationship for the circuit of Figure

6 with R1 = R2.

VREF

DB7

DATA

(8-BIT)

DB0

CS

WR

LDAC

RESET

VREF

3

VDD

R1

R2

+15V

DAC

AD7224

VOUT

+15V

VOUT

R1, R2 = 10kΩ ±0.1%

VSS

AGND

DGND

Figure 6. Bipolar Output Circuit

Table III. Bipolar (Offset Binary) Code Table

DAC Register Contents

MSB

LSB

1111

1111

1000

0001

Analog Output

+V

REF



127

128



+V

REF



1

128



1000

0111

0000

0000

0000

1111

0001

0000

0V

–V

REF



1

128



–V

REF



127

128



–V REF



128

128



=

–V REF

VIN

VREF

VDD

AGND

VIN

VBIAS

DAC

VSS

AD7224

DGND

VOUT

Figure 7. AGND Bias Circuit

MICROPROCESSOR INTERFACE

A15

A8

8085A

8088

WR

ALE

AD7

AD0

ADDRESS BUS

ADDRESS

DECODE

LATCH

EN

CS

LDAC

AD7224*

WR

DB7

DB0

ADDRESS DATA BUS

*LINEAR CIRCUITRY OMITTED FOR CLARITY

Figure 8. AD7224 to 8085A/8088 Interface

A15

A0

6809

6502

R/W

E OR φ2

D7

E OR φ2

D0

D7

D0

ADDRESS BUS

ADDRESS

DECODE

EN

CS

LDAC

AD7224*

WR

DB7

DB0

DATA BUS

*LINEAR CIRCUITRY OMITTED FOR CLARITY

Figure 9. AD7224 to 6809/6502 Interface

A15

A0

Z-80

WR

D7

D0

ADDRESS BUS

ADDRESS

DECODE

CS

LDAC

AD7224*

WR

DB7

DB0

DATA BUS

*LINEAR CIRCUITRY OMITTED FOR CLARITY

AGND BIAS

The AD7224 AGND pin can be biased above system GND

(AD7224 DGND) to provide an offset “zero” analog output

voltage level. Figure 7 shows a circuit configuration to achieve

this. The output voltage, VOUT, is expressed as:

VOUT = VBIAS + D • (VIN)

where D is a fractional representation of the digital word in

DAC register and can vary from 0 to 255/256.

For a given VIN, increasing AGND above system GND will re-

duce the effective VDD–VREF which must be at least 4 V to en-

sure specified operation. Note that VDD and VSS for the AD7224

must be referenced to DGND.

REV. B

–7–

Figure 10. AD7224 to Z-80 Interface

A23

A1

68008

R/W

DTACK

D7

D0

ADDRESS BUS

ADDRESS

DECODE

CS

LDAC

WR

AD7224*

DB7

DB0

DATA BUS

*LINEAR CIRCUITRY OMITTED FOR CLARITY

Figure 11. AD7224 to 68008 Interface

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