AD9040A(RevD) 데이터 시트보기 (PDF) - Analog Devices

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AD9040A
(Rev.:RevD)

10-Bit 40 MSPS A/D Converter

Analog Devices 

AD9040A

0

–65

ENCODE = 40.5MSPS

f1 IN = 2.25MHz @ –7dBFS

f2 IN = 2.35MHz @ –7dBFS

2f1 – f2 = –69.4dBFS

2f2 – f1 = –69.2dBFS

0

–65

ENCODE = 40.5MSPS

ANALOG IN = 2.3MHz

SNR = 55.20dB

SNR (w/o har.) = 55.90dB

SECOND HARMONIC = –75.1dB

THIRD HARMONIC = –73.2dB

0

ENCODE = 40.5MSPS

ANALOG IN = 10.3MHz

SNR = 53.38dB

SNR (w/o har.) = 54.31dB

SECOND HARMONIC =

–64.7dB

THIRD HARMONIC =

–73.7dB

–65

0

2.5

5.0

0

10.0

20.2

0

10.0

20.2

FREQUENCY (MHz)

FREQUENCY (MHz)

FREQUENCY (MHz)

OBSOLETE TPC10. FFTResponse

TPC 11. FFT Response

TPC 12. FFT Response

THEORY OF OPERATION

The AD9040A employs subranging architecture and digital error

correction. This combination of design techniques ensures true

10-bit accuracy at the digital outputs of the converter.

At the input, the analog signal is applied to a track-and-hold

(T/H) that holds the analog value that is present when the

unit is strobed with an encode command. The conversion

process begins on the rising edge of this pulse, which should

have a 50% (± 10%) duty cycle. The minimum encode rate of

the AD9040A is 10 MSPS because of the use of three inter-

nal track-and-hold devices.

The held analog value of the first track-and-hold is applied to a

USING THE AD9040A

Timing

The duty cycle of the encode clock for the AD9040A is critical

for obtaining the rated performance of the ADC. Internal

pulsewidths within the track-and-hold are established by the

encode command pulsewidth; to ensure rated performance, the

duty cycle should be held at 50%. Duty cycle variations of less

than ± 10% will cause no degradation in performance.

Operation at encode rates less than 10 MSPS is not recom-

mended. The internal track-and-hold saturates, causing erroneous

conversions. This track-and-hold saturation precludes clocking

the AD9040A in burst mode. The 50% duty cycle must be

5-bit flash converter and a pair of internal track-and-hold devices

maintained even for sample rates down to 10 MSPS.

(shown in the Functional Block Diagram as a single unit). The The AD9040A provides latched data outputs, with 2 1/2 pipe-

track-and-hold devices pipeline the analog signal to the ampli- line delays. Data outputs are available one propagation delay

fier array through a residue ladder and switching circuit while the

5-bit flash converter resolves the most significant bits (MSB) of

(tPD) after the falling edge of the encode command (see Figure 1).

The length of the output data lines and the loads placed on them

the held analog voltage.

should be minimized to reduce transients within the AD9040A;

When the 5-bit flash converter has completed its cycle, its out-

put activates 1 of 32 ladder switches; these in turn cause the

these transients can detract from the converter’s dynamic per-

formance.

correct residue signal to be applied to the error amplifier array. Voltage Reference

The output of the error amplifier is applied to a 6-bit flash con-

verter whose output supplies the five least significant bits (LSB)

of the digital output along with one bit of error correction for

the 5-bit main range converter.

Decode logic aligns the data from the two converters and pre-

sents the result as a 10-bit parallel digital word. The output

stage of the AD9040A is CMOS. Output data are strobed on

A stable voltage reference is required to establish the 2 V p-p

range of the AD9040A. There are two options for creating this

reference. The easiest and least expensive way to implement it is

to use the (2.5 V) band gap voltage reference which is internal

to the ADC. Figure 3 illustrates the connections for using the

internal reference. The internal reference has 500 µA of extra

drive current that can be used for other circuits.

the trailing edge of the encode command.

The full-scale range of the AD9040A is determined by the refer-

AD9040A

ence voltage applied to the VREF (Pin 6) input. This voltage sets

the internal flash and residue ladder voltage drops; these estab-

VOUT

2.5V

BAND GAP

REFERENCE

lish the value of the LSB. Because of headroom restraints, the

full-scale range cannot be increased by applying a higher than

specified reference voltage. Conversely, a lower reference volt-

age will reduce the full-scale range of the converter but will also

VREF

REF

AMP

REFERENCE

decrease its performance. An internal band gap reference volt-

age of 2.5 V is provided to assure optimum performance over

0.1␮F BPREF

the operating temperature range.

–VS

Figure 3. Using Internal Reference

–8–

REV. D

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