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AD9430-210 데이터 시트보기 (PDF) - Analog Devices
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AD9430-210
12-Bit, 170/210 MSPS 3.3 V A/D Converter
Analog Devices
AD9430-210 Datasheet PDF : 44 Pages
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TIMING DIAGRAMS
CLK+
CLK–
DS+
DS–
t
HDS
INTERLEAVED DATA OUT
PORT A
DA11–DA0
STATIC
t
SDS
14 CYCLES
INVALID
t
PD
N
N+2
PORT B
DB11–DB0
STATIC
INVALID
INVALID
N+1
PARALLEL DATA OUT
PORT A
DA11–DA0
STATIC
PORT B
DB11–DB0
STATIC
DCO–
DCO+
STATIC
INVALID
INVALID
INVALID
INVALID
N
N+1
t
CPD
Figure 2. CMOS Timing Diagram
t
V
N+3
N+2
N+3
AD9430
A
IN
CLK+
CLK–
DATA OUT
DCO+
DCO–
N–1
N
N+1
t
EL
t
EH
1/f
S
t
PD
N–14
N–13
14 CYCLES
N
N+1
t
CPD
Figure 3. LVDS Timing Diagram
Rev. E | Page 9 of 44
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