AD9520-0/PCBZ 데이터 시트보기 (PDF) - Analog Devices

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AD9520-0/PCBZ

12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO

Analog Devices 

AD9520-0

CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)

Table 7.

Parameter

LVPECL ABSOLUTE PHASE NOISE

Min Typ Max Unit

VCO = 2.95 GHz; Output = 2.95 GHz

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

@ 10 MHz Offset

@ 40 MHz Offset

VCO = 2.75 GHz; Output = 2.75 GHz

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

@ 10 MHz Offset

@ 40 MHz Offset

VCO = 2.55 GHz; Output = 2.55 GHz

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

@ 10 MHz Offset

@ 40 MHz Offset

−46

−78

−104

−123

−139

−145

−49

−80

−106

−125

−140

−146

−51

−82

−108

−127

−140

−146

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

Test Conditions/Comments

Internal VCO; direct-to-LVPECL output and for loop

bandwidths < 1 kHz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)

Table 8.

Parameter

LVPECL OUTPUT ABSOLUTE TIME JITTER

VCO = 2.949 GHz; LVPECL = 245.76 MHz; PLL LBW = 63 kHz

VCO = 2.703 GHz; LVPECL = 122.88 MHz; PLL LBW = 63 kHz

VCO = 2.703 GHz; LVPECL = 61.44 MHz; PLL LBW = 63 kHz

Min Typ Max Unit Test Conditions/Comments

Application example based on a typical

setup where the reference source is

clean, so a wider PLL loop bandwidth is

used; reference = 15.36 MHz; R DIV = 1

176

fs rms Integration BW = 200 kHz to 10 MHz

351

fs rms Integration BW = 12 kHz to 20 MHz

158

fs rms Integration BW = 200 kHz to 10 MHz

324

fs rms Integration BW = 12 kHz to 20 MHz

177

fs rms Integration BW = 200 kHz to 10 MHz

330

fs rms Integration BW = 12 kHz to 20 MHz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)

Table 9.

Parameter

LVPECL OUTPUT ABSOLUTE TIME JITTER

VCO = 2.799 GHz; LVPECL = 155.52 MHz; PLL LBW = 1.8 kHz

VCO = 2.703 GHz; LVPECL = 122.88 MHz; PLL LBW = 2.1 kHz

Min Typ Max Unit Test Conditions/Comments

Application example based on a typical

setup where the reference source is

jittery, so a narrower PLL loop bandwidth

is used; reference = 19.44 MHz; R DIV = 162

652

fs rms Integration BW = 12 kHz to 20 MHz

607

fs rms Integration BW = 12 kHz to 20 MHz

Rev. 0 | Page 11 of 84

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