ADMC200 데이터 시트보기 (PDF) - Analog Devices
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ADMC200 Datasheet PDF : 12 Pages
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ADMC200
A0–A13
ADSP-2101/
DMS
ADSP-2105/
ADSP-2115–20MHz IRQ2
ADSP-2171–10MHz RD
ADSP-2181–10MHz WR
CLKOUT
D0–D23
ADDRESS BUS
VDD
ADDRESS
DECODE
EN
A0–A3
CS
IRQ
ADMC200
RD
WR
CLK
D0–D11*
DATA BUS
*NOTE:
BY MAPPING THE ADMC200 DATA BUS TO THE TWELVE HIGHEST BITS
OF THE ADSP DATA BUS, FULL-SCALE OUTPUTS FROM THE ADC
CAN BE REPRESENTED BY ± 1.0 IN FIXED POINT ARITHMETIC.
Figure 11. ADI Digital Signal Processor/Microcomputer
A0–A15
IS
TMS320C20
INTn
TMS320C25
STRB
TMS320C25-50
R/W
ADDRESS BUS
VDD
ADDRESS
DECODE
EN
CLKOUT1
D0–D15
A0–A3
CS
IRQ
ADMC200
RD
WR
CLK
D0–D11
DATA BUS
Figure 12. TI Second-Generation Devices TMS320C20/
C25/C25–50
In the case of the ADSP-2171/2181, the system clock is internally
scaled; a 10 MHz system clock will derive a 20 MHz CLKOUT.
In the case of the TMS320C2x, the CLKOUT1 signal is derived
from the system clock divided by a factor of 4; consequently a
50 MHz TMS320C25-50 will derive a 12.5 MHz CLKOUT1 for
use by the ADMC200.
Note: A pull-up resistor is required on the IRQ (Pin 18) output
from the ADMC200. The STOP (Pin 47) must be tied low if
not in use.
SYSTEM CLOCK FREQUENCY
The nominal range of the input clock for the ADMC200 is
6.25 MHz to 25 MHz. The external CLK frequency can be in-
ternally divided down by 2 by writing to Bit 5 of the SYSCTRL
register. If the external CLK is faster than 12.5 MHz then it is
necessary to internally divide it down.
REGISTER ADDRESSING
Four address lines (A0 through A3) are used in conjunction
with the control lines (CS, WR, RD,) to select registers 0
through 15. The CS and RD control lines are active low. The
registers are given symbolic names.
Table II.
Pin
Function
CS
Enables the ADMC200 register interface
(connect via chip select logic-active low)
RD
Places data from the internal register onto the
data bus
WR
Loads the internal register with data on the
data bus on its positive edge
Name
RHO
PHIP1/VD
PHIP2/VQ
PHIP3
RHOP
PWMTM
PWMCHA
PWMCHB
PWMCHC
PWMDT
PWMPD
SYSCTRL
Table III. Write Registers
A3 A2 A1 A0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Register Function
Load RHO (ρ) and Start Reverse Transform
Reverse Rotation Direct Input/Forward Direct Input
Reverse Rotation Direct Input/Forward Direct Input
Reverse Rotation Direct Input
Load RHOP(ρ) and Start Forward Transform
PWM Master Switching Period
PWM Channel A On-Time
PWM Channel B On-Time
PWM Channel C On-Time
PWM Programmable Deadtime (7-Bit Register)
PWM Pulse Deletion Value (7-Bit Register)
Reserved
Reserved
System Control
Reserved
Reserved
–10–
REV. B
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