ADMC200 데이터 시트보기 (PDF) - Analog Devices
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ADMC200 Datasheet PDF : 12 Pages
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ADMC200
Table I. Timing Specifications (VDD = 5 V ؎ 5%; TA = –40؇C to +85؇C)
Number
Symbol
Timing Requirements
Min
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 9
16
17
18
19
20
21
22
23
24
tperclk
tpwhclk
tpwlclk
tsucsb_wrb
tsuaddr_wrb
tsudata_wrb
thdwrb_data
thdwrb_addr
thdwrb_csb
tpwlwrb1
tpwhwrb1
thdwrb_clk_h1
tsuwrb_clk_h1
tsuwrb_clk_l1
thdclk_wrb_l1
tsucsb_rdb
tsuaddr_rdb
thdrdb_addr
thdrdb_csb
tpwlrdb
tpwhrdb
tsurdb_clk_h
thdrdb_clk_h
tpwlresetb
CLK Period
CLK Pulsewidth, High
CLK Pulsewidth, Low
CS Low before Falling Edge of WR
ADDR Valid before Falling Edge of WR
DATA Valid before Rising Edge of WR
DATA Hold after Rising Edge of WR
ADDR Hold after Rising Edge of WR
CS Hold after Rising Edge of WR
WR Pulsewidth, Low
WR Pulsewidth, High
WR Low after Rising Edge of CLK
WR High before Rising Edge of CLK
WR High before Falling Edge of CLK
WR High after Falling Edge of CLK
CS Low before Falling Edge of RD
ADDR Valid before Falling Edge of RD
ADDR Hold after Rising Edge of RD
CS Hold after Rising Edge of RD
RD Pulsewidth, Low
RD Pulsewidth, High
RD Low before Rising Edge of CLK
RD Low after Rising Edge of CLK
RESET Pulsewidth, Low
40
20
20
0
0
13
4.5
4.5
4.5
20
20
7
7
10
10
0
0
0
0
20
20
7.5
7.5
2 × tperclk
NOTE
1All WRITES to the ADMC200 must occur within 1 system clock cycle (0 wait states).
Number
Symbol
Switching Characteristics
Min
25
tdlyrdb_data
DATA Valid after Falling Edge of RD
26
thdrdb_data
DATA Hold after Rising Edge of RD
0
Max
160
Max
23
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
CLK
1
2
3
Figure 1. Clock Input Timing
CLK
24
RESET
Figure 2. Reset Input Timing
CLK
CS
12
15 13
9
8
A0–A3
WR
11
14
10
DATA
4
6
5
7
NOTE:
ALL WRITES TO THE ADMC200 MUST OCCUR WITHIN
ONE SYSTEM CLOCK CYCLE (i.e. 0 WAIT STATES)
Figure 3. Write Cycle Timing Diagram
REV. B
–3–
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