ADUC812(1999) 데이터 시트보기 (PDF) - Analog Devices
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ADUC812 Datasheet PDF : 31 Pages
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ADuC812
ON-CHIP PERIPHERALS
The following sections give a brief overview of the various sec-
ondary peripherals also available on-chip. A quick reference to
the various SFR configuration registers used to control these
peripheral functions is given on the following pages.
PARALLEL I/O PORTS 0–3
The ADuC812 uses four general purpose data ports to exchange
data with external devices. In addition to performing general
purpose I/O, some ports are capable of external memory opera-
tions; others are multiplexed with an alternate function for the
peripheral features on the device. In general, when a peripheral
sharing a port pin is enabled, that pin may not be used as a
general purpose I/O pin.
Ports 0, 2 and 3 are bidirectional while Port 1 is an input only
port. All ports contain an output latch and input buffer, the I/O
Ports will also contain an output driver. Read and Write accesses
to Port 0–3 pins are performed via their corresponding special
function registers.
Port pins on Ports 0, 2 and 3 can be independently configured
as digital inputs or digital outputs via the corresponding port
SFR bits. Port 1 pins however, can be configured as digital
inputs or analog inputs only, Port 1 digital output capability is
not supported on this device.
SERIAL I/O PORTS
UART Interface
The serial port is full duplex, meaning it can simultaneously
transmit and receive. It is also receive-buffered, meaning it can
commence reception of a second byte before a previously re-
ceived byte has been read from the receive register. However, if
the first byte still hasn't been read by the time reception of the
second byte is complete, one of the bytes will be lost.
The physical interface to the serial data network is via Pins
RxD(P3.0) and TxD(P3.1) and the serial port can be configured
into one of four modes of operation.
Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is an industry standard
synchronous serial interface that allows eight bits of data to be
synchronously transmitted and received simultaneously. The
system can be configured for Master or Slave operation.
I2C-Compatible Serial Interface
The ADuC812 supports a 2-wire serial interface mode that is
I2C-compatible. This interface can be configured to be a Soft-
ware Master or Hardware Slave and is multiplexed with the SPI
serial interface port.
TIMERS/COUNTERS
The ADuC812 has three 16-bit Timer/Counters, namely: Timer 0,
Timer 1 and Timer 2. The Timer/Counter hardware has been
included on-chip to relieve the processor core of the overhead
inherent in implementing timer/counter functionality in soft-
ware. Each Timer/Counter consists of two 8-bit registers THx
and TLx (x = 0, 1 and 2). All three can be configured to operate
either as timers or event counters.
In “Timer” function, the TLx register is incremented every
machine cycle. Thus one can think of it as counting machine
cycles. Since a machine cycle consists of 12 oscillator periods,
the maximum count rate is 1/12 of the oscillator frequency.
In “Counter” function, the TLx register is incremented by a
1-to-0 transition at its corresponding external input pin, T0, T1
or T2.
ON-CHIP MONITORS
The ADuC812 integrates two on-chip monitor functions to
minimize code or data corruption during catastrophic program-
ming or other external system faults. Again, both monitor func-
tions are fully configurable via the SFR space.
WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device reset
within a reasonable amount of time if the ADuC812 enters an
erroneous state, possibly due to a programming error, electrical
noise or RFI. The Watchdog function can be permanently dis-
abled by clearing WDE (Watchdog Enable) bit in the Watchdog
Control (WDCON) SFR. When enabled, the watchdog circuit
will generate a system reset if the user program fails to refresh
the watchdog within a predetermined amount of time. The
watchdog reset interval can be adjusted via the SFR prescale bits
from 16 to 204 ms.
POWER SUPPLY MONITOR
The Power Supply Monitor generates an interrupt when
the analog (AVDD) or digital (DVDD) power supplies to the
ADuC812 drop below one of five user-selectable voltage trip
points from 2.6 V to 4.6 V The interrupt bit will not be cleared
until the power supply has returned above the trip point for at
least 256 ms.
This monitor function ensures that the user can save working
registers to avoid possible data corruption due to the low supply
condition, and that code execution will not resume until a “safe”
supply level has been well established. The supply monitor is
also protected against spurious glitches triggering the interrupt
circuit.
QuickStart DEVELOPMENT SYSTEM
The QuickStart Development System is a full featured, low cost
development tool suite supporting the ADuC812. The system
consists of the following PC-based (Win95-compatible) hard-
ware and software development tools.
Code Development: Full Assembler and C Compiler
(2K Code Limited)
Code Functionality: ADSIM812, Windows Code Simulator
Code Download: FLASH/EE UART-Serial Downloader
Code Debug: Serial Port Debugger
Misc: System includes CD-ROM documentation, power supply
and serial port cable.
REV. 0
Figure 15. Typical QuickStart System Configuration
–17–
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