ADV7123KST50 데이터 시트보기 (PDF) - Analog Devices
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ADV7123KST50 Datasheet PDF : 20 Pages
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ADV7123
5 V TIMING SPECIFICATIONS1 (VAA = 5 V ؎ 5%2, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications TMIN to TMAX3,
unless otherwise noted, TJ MAX = 110؇C.)
Parameter
Min
Typ
Max
Unit
Condition
ANALOG OUTPUTS
Analog Output Delay, t6
Analog Output Rise/Fall Time, t74
Analog Output Transition Time, t85
Analog Output Skew, t96
5.5
ns
1.0
ns
15
ns
1
2
ns
CLOCK CONTROL
fCLK7
fCLK7
fCLK7
Data and Control Setup, t1
Data and Control Hold, t2
Clock Pulsewidth High, t4
Clock Pulsewidth Low t5
Clock Pulsewidth High t4
Clock Pulsewidth Low t5
Clock Pulsewidth High t4
Clock Pulsewidth Low t5
Pipeline Delay, tPD6
PSAVE Up Time, t106
0.5
50
0.5
140
0.5
240
0.5
1.5
1.875
1.875
2.85
2.85
8.0
8.0
1.0
1.0
1.0
2
10
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
ns
50 MHz Grade
140 MHz Grade
240 MHz Grade
fCLK_MAX = 240 MHz
fCLK_MAX = 240 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 50 MHz
fCLK_MAX = 50 MHz
NOTES
1Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
2These maximum and minimum specifications are guaranteed over this range.
3Temperature range: TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz.
4Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5Measured from 50% point of full-scale transition to 2% of final value.
6Guaranteed by characterization.
7fCLK max specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.
Specifications subject to change without notice.
–6–
REV. B
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