LC7073 데이터 시트보기 (PDF) - SANYO -> Panasonic

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LC7073

Error Detection and Correction ICs for RDS Demodulators

SANYO -> Panasonic 

LC7073, 7073M

VDD

VDD

RES

＋

C=0.1µF

Figure 8. Reset input

4.5V

VDD

Start point

RES

0.8VDD

1.125V

(0.25VDDmin)

Oscillator stabilization

time (10 to 100 ms)

Figure 9. Supply rise time vs. reset delay

A minimum delay of 10 ms should be allowed for oscillator stabilization. A 10 to 100 ms reset delay is generated using

a 0.1 µF reset capacitor, C. A larger capacitor should be used if the supply rise time is longer.

Figure 10. System block diagram

Device Comparison

The LC7070N, LC7070M and LC7071NM have identical basic functions, pinouts and input/output timing to those of the

LC7073 and LC7073M. Their respective packages and output circuitry are compared in table 3.

Table 3. Device comparison

Device

LC7070N

LC7070NM

LC7071NM

LC7073

LC7073M

Package

18-pin DIP

18-pin MFP

18-pin MFP

18-pin DIP

18-pin MFP

Open-drain

Output type

Totem-pole using MOS transistors

The differences in output data format between the LC7070N/LC7070NM/LC7071NM and LC7073/LC7073M are as

follows.

Offset Words E and F

The LC7070N/LC7070NM/LC7071NM recognizes offset words E and F and performs group sync detection. The LC7073/

LC7073M does not recognize offset words E and F–it only detects A, B, C, C’ and D.

Input Data Bits

If all data bits are 0, the LC7070N/LC7070NM/LC7071NM only recognizes offset word E. The LC7073/LC7073M does

not recognize the offset word E block. No sync detection occurs if all input data bits are 0. Once data cutoff has been

determined, output data stops and the sync cutoff sequence begins.

No.3932–8/9

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