AMIS-30511 데이터 시트보기 (PDF) - ON Semiconductor

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AMIS-30511

Micro-Stepping Motor Driver

ON Semiconductor 

AMIS−30511

Functional Description

H−Bridge Drivers

A full H−bridge is integrated for each of the two stator

windings. Each H−bridge consists of two low−side and two

high−side N−type MOSFET switches. Writing logic ‘0’ in

bit <MOTEN> disables all drivers (high−impedance).

Writing logic ‘1’ in this bit enables both bridges and current

can flow in the motor stator windings.

In order to avoid large currents through the H−bridge

switches, it is guaranteed that the top− and bottom−switches

of the same half−bridge are never conductive

simultaneously (interlock delay).

A two−stage protection against shorts on motor lines is

implemented. In a first stage, the current in the driver is

limited. Secondly, when excessive voltage is sensed across

the transistor, the transistor is switched−off.

In order to reduce the radiated/conducted emission,

voltage slope control is implemented in the output switches.

The output slope is defined by the gate−drain capacitance of

output transistor and the (limited) current that drives the

gate. There are two trimming bits for slope control

(Table 23: SPI Control Parameter Overview EMC[1:0]).

The power transistors are equipped with so−called “active

diodes”: when a current is forced through the transistor

switch in the reverse direction, i.e. from source to drain, then

the transistor is switched on. This ensures that most of the

current flows through the channel of the transistor instead of

through the inherent parasitic drain−bulk diode of the

transistor.

Depending on the desired current range and the

micro−step position at hand, the Rdson of the low−side

transistors will be adapted such that excellent current−sense

accuracy is maintained. The Rdson of the high−side

transistors remain unchanged, see Table 4: DC Parameters

for more details.

PWM Current Control

A PWM comparator compares continuously the actual

winding current with the requested current and feeds back

the information to a digital regulation loop. This loop then

generates a PWM signal, which turns on/off the H−bridge

switches. The switching points of the PWM duty−cycle are

synchronized to the on−chip PWM clock. The frequency of

the PWM controller can be doubled and an artificial jitter

can be added (Table 12: SPI Control Register 1). The PWM

frequency will not vary with changes in the supply voltage.

Also variations in motor−speed or load−conditions of the

motor have no effect. There are no external components

required to adjust the PWM frequency.

Automatic Forward and Slow−Fast Decay

The PWM generation is in steady−state using a

combination of forward and slow−decay. The absence of

fast−decay in this mode, guarantees the lowest possible

current−ripple “by design”. For transients to lower current

levels, fast−decay is automatically activated to allow

high−speed response. The selection of fast or slow decay is

completely transparent for the user and no additional

parameters are required for operation.

Icoil

Set value

0

TPWM

Actual value

t

Forward & Slow Decay

Fast Decay & Forward

Forward & Slow Decay

Figure 5. Forward and Slow/Fast Decay PWM

In case the supply voltage is lower than 2*Bemf, then the

duty cycle of the PWM is adapted automatically to >50% to

maintain the requested average current in the coils. This

process is completely automatic and requires no additional

parameters for operation. The over−all current−ripple is

divided by two if PWM frequency is doubled (Table 12: SPI

Control Register 1).

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